4-Layer PCB Design for Servo Controller
Thought for 8 sec
I’ll replace U3 and update R19, but first I need to identify the intended replacement parts/values from the project state and any uploaded reference. I’ll inspect U3/R19, check available replacements, then preserve or restore their connections after the swap.
Worked for 50 sec
I inspected U3 and R19. U3 is currently TXS0102DCTR wired as the 3.3 V ↔ 5.1 V I2C level shifter, and R19 is the 4.7 kΩ SDA_5V pull-up to 5V1_LOGIC.
I’m blocked because replacing U3 requires the exact new level-shifter part/MPN, and replacing R19 requires the intended resistor value/package or whether it should be removed. Send the replacement part for U3 and the intended change for R19 — for example: “replace U3 with PCA9306” and “change R19 to 10 kΩ / remove R19.”
remove both and place new one
Thought for 14 sec
I’ll remove the existing level shifter and pull-up resistor, then add a fresh level-shifter component back in place and restore its I2C/power connections without the R19 pull-up.
Worked for 11 mins 3 sec
Done. Removed the old U3 and R19, added a fresh U3 TXS0102DCTR, restored its SDA/SCL, power, OE, and GND connections, and placed it back in the interface cluster near J1/J2 and the related resistors.
Note: R19 is now removed, so the SDA_5V pull-up is gone; SCL_5V still has R20. The focused check did not report U3/R19-related issues, but the broader project may still have the previous layout/routing issues.
Add SDA pull-up
Check level shifter
Check pull-up values
Move R20 closer
Project Specification
Goal
Design a compact 4-layer PCB for a dual PCA9685 servo controller interfaced with a Raspberry Pi 5 on the 3.3 V I2C side and an STM32 Nucleo on the 5.1 V logic side.
Required rails
- 3.3 V reference from Raspberry Pi 5 header for TXS0102 LV side.
- 5.1 V logic rail from buck converter for TXS0102 HV side, PCA9685 VCC, STM32 Nucleo 5V pin, OE pull-up, and HV I2C pull-ups if used.
- 6.0 V dedicated servo rail sized for 20 A load with 2 oz / 70 um copper.
- Common GND across Pi, Nucleo, logic, and servo rails.
Required ICs and interfaces
- TXS0102 level translator: A1=SDA_LV, A2=SCL_LV, B1=SDA_5V, B2=SCL_5V.
- PCA9685 chip 1: address 0x40, all address pins to GND.
- PCA9685 chip 2: address 0x41, A0 to 5.1 V, remaining address pins to GND.
- STM32 Nucleo header: PB8/D15=SCL_5V, PB9/D14=SDA_5V, PC7/D9=OE, PA0/A0=VSense divider midpoint, 5V fed by 5.1 V logic rail.
Required passives
- 17x 220 ohm PWM series resistors, one for each used PCA9685 output.
- 1x 10k OE pull-up to 5.1 V.
- VSense divider to PA0/A0.
- Decoupling capacitors for IC supplies and bulk capacitance on logic/servo rails.
- 4.7k I2C pull-ups on HV side only if allowed/needed after TXS0102 datasheet check.
Layout requirements
- 4-layer PCB.
- Inner GND plane and inner power plane.
- 2 oz (70 um) copper for 20 A servo load paths.
- Compact functional placement: Pi/TXS0102, Nucleo/VSense, PCA9685/series resistors/servo outputs.
Goal
Required rails
Required ICs and interfaces
Required passives
Layout requirements