Power Section Design Update

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  1. Minimum clearance design rule:
  • 0.0889 mm (3.5 mil) minimum keepout, marked !important.
  • General preferred keepout: 0.0965 mm (3.8 mil).
  • Separate HV-net rules require 3.0 mm clearance for the designated 415 V nets.
  1. Smallest different-net copper gap:
  • Exact measured value and net pair are not exposed by the available net-aware layout/DRC data.
  • DRC reports no different-net overlap or clearance violation.
  • Previously measured sub-0.15 mm gaps were same-net geometry:
    • GND ↔ GND: ~0.000021 mm
    • VBIAS_1V65 ↔ VBIAS_1V65: 0.0635 mm
  1. Different-net pairs below 0.15 mm:
  • None reported by DRC.
  • An exact exhaustive geometric list cannot be confirmed with the available net-aware measurement output.
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Change the HV BOARD minimum clearance DESIGN RULE from 0.0889mm to 0.15mm (6 mil). Keep the separate 3.0mm rule on the 415V nets unchanged. Do NOT route or modify copper yet - just change the rule.
Then report:
  1. How many DIFFERENT-net copper pairs now violate the 0.15mm rule?
  2. List each one: the two nets, the layer, and the exact gap in mm.
  3. Confirm the 415V nets still show >= 3.0mm.

flux

I’ll change only the global minimum copper clearance to 0.15 mm, preserve the separate 3.0 mm HV rules, then run DRC and list any new different-net violations.

flux

Global minimum copper clearance changed to 0.15 mm (6 mil). No copper, routing, or placement was modified.
  1. Different-net copper pairs violating 0.15 mm: 0
  2. Violating pairs: none
  3. The separate 3.0 mm rules remain applied to all designated 415 V nets; 0 HV clearance violations are reported.
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Files

Schematic

Layout

Preview

Board Bring-Up Plan — 12V Multi-Rail Power Section
Prerequisites
  • Equipment: current-limited bench supply, multimeter, oscilloscope, thermal camera or IR thermometer if available.
  • Start with no downstream loads connected to +4V, +5V, or +3V3.
  • Initial current limit: 12V input at 100mA, then increase only after rails pass.
  • Safety note: +3V3 load current also passes through U_5V because U_3V3 is fed from +5V; verify U_5V temperature under combined worst-case load.
1. Visual Inspection
  • Confirm J_PWR pin 1 routes to +12V and pin 2 routes to GND.
  • Confirm D_TVS is across +12V and GND.
  • Confirm polarized capacitors C_IN, C_4V, C_4V_BULK, C_5V, and C_3V3 are installed with positive terminals on their rails.
  • Confirm C_4V_BULK is installed as 470uF low-ESR electrolytic on +4V close to the A7672SA power pins during layout.
  • Confirm U_5V and U_3V3 SOT-223 tabs are on their respective outputs and have the required copper/heatsinking in layout. Do not short the tab pads to GND; AMS1117 tab is VOUT.
2. Power Rail Verification

Table

RailSourceExpected VoltageToleranceMeasure AtInitial Current LimitPass Criteria
+12VJ_PWR pin 112V inputSupply settingJ_PWR pin 1 / C_IN P1100mANo excessive input current or heating
+4VU_4V LMR33630 buck via L14.0V+/-5% initial checkC_4V P1, C_4V_BULK P1, or L1 pin 2100mA, then 2A burst-capable validation3.8V to 4.2V and stable during burst load
+5VU_5V AMS1117-5.05.0V+/-3% initial checkC_5V P1 / U_5V VOUT100mA, then 150mA combined worst-case check4.85V to 5.15V and stable
+3V3U_3V3 AMS1117-3.33.3V+/-3% initial checkC_3V3 P1 / U_3V3 VOUT100mA max-load check3.20V to 3.40V and stable
GNDCommon return0V referenceN/AJ_PWR pin 2N/AContinuity to all regulator grounds
Procedure:
  1. With power off, measure resistance from +12V, +4V, +5V, and +3V3 to GND.
  2. Apply 12V through a current-limited bench supply at 100mA.
  3. Measure +12V, then +4V, +5V, and +3V3 in sequence.
  4. Validate +3V3 at 100mA maximum and direct +5V at 50mA maximum; remember U_5V sees about 150mA total when both are at maximum.
  5. Check U_5V and U_3V3 temperature after 1 minute and again after thermal soak under intended load.
  6. Use an oscilloscope to check +4V buck ripple at C_4V_BULK P1 during A7672SA-like 2A burst loading.
3. Critical Power Signals

Table

SignalNet NameExpected StateMeasure AtNotes
Buck enable+12V / U_4V ENHigh when input appliedU_4V ENEN is tied to VIN for always-on operation
Buck feedbackFB_4VAbout 1.0V in regulationU_4V FBR_FB_TOP 100k and R_FB_BOT 33.2k set about 4.01V
Buck switch nodeSW_4VSwitching waveformU_4V SW / L1 pin 1Do not probe without a short ground spring
BootstrapBOOT_4VPulsed above SWC_BOOTC_BOOT is 100nF from BOOT to SW
U_4V VCCVCC_U_4VInternal bias railC_VCC P1C_VCC is 1uF to GND
4. Connector Tests

Table

ConnectorTypePins to VerifyTest Method
J_PWR2-pin screw terminalPin 1 +12V, pin 2 GNDContinuity and polarity check before applying power
5. Functional Validation

Table

TestComponents InvolvedInputExpected OutputPass Criteria
Input protection continuityJ_PWR, D_TVS, C_INNo powerD_TVS across +12V/GND, no short at 12V railHigh resistance from +12V to GND
4V buck regulation and burst supportU_4V, L1, C_BOOT, C_4V, C_4V_BULK, feedback divider12V input, 200mA average / 2A burst load+4V rail3.8V to 4.2V stable during representative burst load
5V LDO regulationU_5V, C_5V_IN, C_5V12V input, up to 150mA total through U_5V+5V rail4.85V to 5.15V stable
3V3 LDO regulationU_3V3, C_3V3_IN, C_3V3+5V rail, up to 100mA+3V3 rail3.20V to 3.40V stable
Thermal sanity checkU_5V, U_3V3Intended maximum loadStable temperatureJunction estimate stays below 125C
6. Expected Measurements Reference

Table

MeasurementLocationExpected ValueInstrument
+12V inputJ_PWR pin 1 / C_IN P112VDMM
+4V railC_4V_BULK P1 or C_4V P14.0V nominalDMM / oscilloscope
FB_4VU_4V FBAbout 1.0VDMM
+5V railC_5V P15.0V nominalDMM
+3V3 railC_3V3 P13.3V nominalDMM
U_5V dissipationU_5V packageAbout 0.63W typical, 1.05W worst-case from combined +5V/+3V3 loadsThermal camera / calculation
U_3V3 dissipationU_3V3 packageAbout 0.10W typical, 0.17W worst-caseThermal camera / calculation
Pass/Fail Summary

Table

Test SectionResultNotes
Visual Inspection[ ] Pass / [ ] Fail
Power Rails[ ] Pass / [ ] Fail
Critical Power Signals[ ] Pass / [ ] Fail
Connector Tests[ ] Pass / [ ] Fail
Functional Validation[ ] Pass / [ ] Fail
Board Status: [ ] Ready for downstream-circuit bring-up / [ ] Requires rework

  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. Critical Power Signals

  • 4. Connector Tests

  • 5. Functional Validation

  • 6. Expected Measurements Reference

  • Pass/Fail Summary