24V AC to Low-Noise DC Supply

flux

The existing 24 VAC → 5 V/3.3 V supply was completed and verified earlier. The follow-on executor reports adding:
  • ESP32-S3-WROOM-1-N16R8
  • Native USB-C programming with BOOT/RESET
  • Y1, W1, G, and O/B relay-control channels
  • R/Rh, Rc, C, and HVAC output terminals
Remaining work
  • Independently verify the new circuitry, GPIO assignments, relay defaults, USB backfeed protection, power budget, firmware document, and ERC results.
  • Review any executor-reported caveats.
Execution stopped because no ACUs are currently available; the newly added circuitry should be treated as pending final verification.
Received notification from "ESP32 Thermostat Controller" that it finished — picking the work back up.

flux

The executor completed the ESP32 thermostat controller addition, but I cannot perform the required independent reconciliation because no ACUs are available.
Reported as added
  • ESP32-S3-WROOM-1-N16R8 module
  • Native USB-C programming
  • BOOT and RESET controls
  • Four relay channels: Y1, W1, G, and O/B
  • HVAC terminals including R/Rh, Rc, and C
Still requires verification
  • ERC and complete net connectivity
  • USB-C CC resistors and USB power/backfeed behavior
  • GPIO selection versus ESP32-S3 boot-strapping pins
  • Relay flyback protection and safe power-up defaults
  • Contact routing from R/Rh or Rc to each HVAC output
  • Updated 3.3 V/5 V power and thermal budgets
Do not manufacture the board until those checks are completed.
Verify controller implementation
Check USB and power
Review HVAC relay safety
Document verification results
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Files

Schematic

Layout

Preview

U1
C5
Capacitance
0.1uF
C14
Capacitance
100nF
C1
Capacitance
470uF
C9
Capacitance
22uF
C13
Capacitance
22uF
C11
Capacitance
22uF
F1
FB1
J3
C12
Capacitance
22uF
J1
C17
Capacitance
10uF
C2
Capacitance
100nF
C8
Capacitance
100nF
C16
Capacitance
10uF
C15
Capacitance
10uF
C6
Capacitance
0.1uF
C19
Capacitance
1uF
J2
C10
Capacitance
22uF
C7
Capacitance
1uF
C18
Capacitance
1uF
BR1
C4
Capacitance
4.7µF
R3
Resistance
20kΩ
R2
Resistance
220kΩ
C3
Capacitance
4.7µF
L1
Inductance
8.2uH
R1
Resistance
100kΩ
U2
Board Bring-Up Plan
Safety and setup
Use a current-limited, isolated 24 VAC bench source for first power-up; do not begin with the full 75 VA transformer. Confirm F1 is 1 A time-lag and verify that DC GND has no continuity to either AC input terminal.
Unpowered checks
  1. Inspect BR1 polarity and C1 electrolytic polarity.
  2. Measure resistance from VRECT to GND; verify it is not a short and trends toward approximately the 100 kΩ bleeder value as capacitors charge.
  3. Measure +5V-to-GND and +3V3-to-GND for shorts.
  4. Verify U1 and U2 exposed pads are soldered and connected to the ground plane.
  5. Confirm U1 bootstrap capacitor is connected between BOOT and SW, not BOOT and GND.
Staged power tests
  1. Apply 12 VAC with a 100–200 mA current limit and no output loads. Verify VRECT is approximately 15–16 V and U1 is near its UVLO start threshold.
  2. Raise to 18 VAC. Verify VRECT is present, +5V is 4.95–5.05 V, and +3V3 is near 3.3 V.
  3. Raise to 24 VAC. Record VRECT ripple, +5V ripple, +3V3 ripple, input RMS current, and temperatures.
  4. Load +3V3 to 250 mA for at least 30 minutes. Pass if U2 remains in regulation and junction/case temperature margin is acceptable for the enclosure ambient.
  5. Apply 700 mA pulses representative of ESP32-S3 radio peaks. Pass if +3V3 stays within the system tolerance and U2 does not enter current limit or thermal shutdown.
  6. Load +5V to 1 A while maintaining 250 mA on +3V3. Confirm regulation and measure F1, BR1, U1, L1, and U2 temperatures.
  7. Perform short-duration combined peak testing: +5V at 1 A with +3V3 pulsed to 700 mA. Confirm no UVLO cycling or excessive VRECT droop.
Protection tests
  • Remove AC and verify the VRECT reservoir discharges with an approximately 47-second time constant.
  • Verify F1 opens safely under a controlled downstream fault; never perform this test with an unrestricted source.
  • Sweep AC input over the expected transformer tolerance and confirm VRECT remains below 42 V in the intended installation.
Pass/fail criteria
  • No continuity between GND and either AC input.
  • No unresolved shorts or reversed polarized components.
  • +5V remains within 4.95–5.05 V at steady state.
  • +3V3 remains suitable for ESP32-S3 operation during specified continuous and pulse loads.
  • No regulator thermal shutdown, UVLO oscillation, fuse nuisance opening, or component exceeding its thermal limit.
  • Measured VRECT stays below the 42 V design assumption; otherwise stop and revise the protection/regulator voltage margin.

  • Safety and setup

  • Unpowered checks

  • Staged power tests

  • Protection tests

  • Pass/fail criteria