Paused. I’ll stop the active redesign thread and leave the project at its current saved state; the CR1632-to-high-rate-LiPo conversion may be partially applied, so I’ll inspect and reconcile it before resuming later.
Paused as requested. The rechargeable-cell redesign executor was stopped before completing a verified handoff, so no changes are being accepted as final.
When resumed, I’ll first inspect any partial schematic mutations, then continue the high-rate LiPo conversion and independent electrical audit.
The schematic is a factory-tabbed CR1632 primary-cell prototype. Rechargeable LiPo, inductive charging, receive-coil, charger, and charge-indication circuitry are removed. UWB, BLE, SWD, and the open-drain-safe DW3210 reset circuit remain.
U6 MAX40200AUK+T provides explicit low-loss reverse-current isolation between the pulse reservoir and the primary cell. The SOT-23-5 pinout is VDD=1, GND=2, EN=3, NC=4, OUT=5. It supports 1 A continuous current; the first tabulated SOT-23 forward-drop point is 32 mV typical / 65 mV maximum at 100 mA. Enabled quiescent current is approximately 7 µA typical and 18 µA maximum, so U6 is a material battery-life cost in this prototype.
R21 = 330 Ω limits fresh-cell initial reservoir charging to approximately 9.7 mA at 3.2 V. Initial dissipation is approximately 31 mW, below its 0.1 W rating.
C53 = SCM5R5355B, a real library/BOM component: 3.5 F, 5.5 V, −20/+80%, 160 mΩ maximum ESR at 1 kHz, 20 × 10 × 22 mm, 5.5 mm lead spacing. The available datasheet states only “low leakage current” and does not give a numeric leakage, DC ESR, peak-current, or pulse-power limit. It is therefore a tall bench/prototype reservoir, not a compact release-qualified part.
U3 TPS63900 remains configured for 2.7 V with unlimited converter input-current programming. R21, not CFG2, limits the CR1632 charging path; limiting U3 to 10 mA would prevent the reservoir from delivering the radio pulse.
Startup is bounded by R21, U3 UVLO, and the converter soft-start. The reservoir RC time constant is approximately 1155 s. From an empty reservoir and a 3.0 V cell, reaching the 1.8 V converter operating threshold takes roughly 18 minutes; approximately 95% charge takes roughly 58 minutes. Cold-start and brownout behavior must be tested.
UWB corrections
U4 is DW3210TR13, a non-PDoA DW3000-family variant.
RF2 is now correctly shunt-terminated by R22 = 50 Ω to GND. The PCB connection from U4 RF2 to R22 must be a controlled 50 Ω trace; TP12 may remain as a probe point only if its stub is kept electrically short. The manufacturer guidance for non-PDoA use is to omit the 2 pF series capacitor and use a 50 Ω PCB trace to a 50 Ω ground termination.
RF1 and the existing primary UWB antenna/matching network are unchanged.
Typical DW3000 TWR figures used for scheduling are 48 mA TX for 170 µs, 78 mA RX for 170 µs, 18 mA idle, and 260 nA deep sleep.
For measurement, firmware drives P0.02 LOW, waits for settling, samples P0.03/AIN1, then returns P0.02 and the ADC input to high-impedance/disconnected states.
Divider current while enabled is approximately 2.4 µA at 3.2 V.
ADC voltage is approximately 0.794 V at 3.2 V battery and 0.496 V at 2.0 V battery.
Firmware should use a SAADC range comfortably above 0.8 V and the longest practical acquisition time. Exact source-resistance/acquisition performance remains a bench-validation item because the narrow datasheet retrieval did not produce citable limits.
When disabled, the top resistor limits any protection-clamp current; verify sleep leakage on hardware.
Bounded burst and recharge envelope
Firmware requirement for this prototype:
Maximum UWB activity window: 10 ms per ranging burst.
Minimum interval: 10 seconds between bursts; longer intervals preferred.
Do not overlap maximum-power BLE transmission with UWB RX/TX.
Conservative pulse check at 100 mA on the 2.7 V output for 10 ms:
output energy: 2.7 mJ;
at 1.8 V reservoir and 80% efficiency, input charge is approximately 1.88 mC;
3.5 F capacitive droop is approximately 0.54 mV;
at approximately 188 mA input current, the specified 160 mΩ ESR contributes approximately 30 mV instantaneous drop.
The reservoir has ample theoretical pulse margin. At one burst per 10 seconds, the worst-case reflected average recharge demand is about 0.19 mA, causing about 62 mV average drop across R21. The dominant unknown is not capacitance; it is the reservoir’s unquantified leakage, cold behavior, and physical size.
Status indication decision
No status LED was restored. A continuously biased LED or divider would materially worsen the coin-cell budget. If indication is required later, use an MCU-driven LED with a very short, infrequent pulse and re-run the battery budget.
Completion and blockers
Table
Item
Status
RF2 50 Ω termination
Completed in schematic
Real pulse reservoir in BOM
Completed for bench prototype
Reverse-current blocking
Completed with U6
Controlled startup/current limiting
Implemented through U6, R21, U3 UVLO/soft-start; cold-start test still required
Battery-voltage measurement
Completed with switched divider
Burst/recharge bounds
Defined: 10 ms maximum, 10 s minimum interval
Reservoir leakage and pulse qualification
Blocked: available SCM datasheet has no numeric leakage/DC-ESR/pulse rating
Compact mechanical fit
Blocked: C53 is 20 × 10 × 22 mm and is not compatible with the intended thin folded tracker
PCB reconciliation
Unattempted by instruction; new/replaced parts are not placed or routed
The architecture is credible for a bench test of CR1632 pulse buffering, but it is not a compact product release until a thin reservoir with quantified leakage, DC ESR, pulse life, and shock/mechanical data replaces C53.