Project Specification
Active scope and status — 2026-10-08
Current FC:
/datiyow499/f405-flight-controller-prototype . Independent F405 compatible prototype, NOT an exact SpeedyBee copy. Separate ESC project remains untouched:
/setej72878/four-channel-55a-esc-prototype . Stop at schematic checkpoint; no PCB sizing/placement/routing performed.
Actual schematic now78 components/68 nets (was36/27). All intended active-scope logical interface blocks are present. Final repeated ERC has12 remaining source-inference errors individually justified in interface-and-firmware-gates; no floating-pin error remains. This is a connected schematic checkpoint, not unconditional electrical, firmware, manufacturing or flight release. See that file for validation limits and exact additions.
Intended use
Bench development, then multirotor integration only after custom firmware and assembled-board validation. Propellers removed throughout bring-up. Compact SMD design; 2.54mm prototype headers deliberately trade density/height for accessible wiring. Their fit into39mm envelope is not yet proven.
Mechanical requirements
FC target39x39mm,30.5x30.5mm mounting centers, reference4.9mm assembly height and4mm side-open holes. Notch geometry and absolute original pad positions remain unresolved. Header assembly height is not claimed to reproduce the reference4.9mm. Separate ESC commercial40.9x44.9x8mm envelope includes heatsink, not a bare PCB fabrication drawing.
Implemented electrical architecture
USB VBUS -> F1 -> D1 -> CORE_5V_OR -> U4 logic3V3 and U5 independent3V3_IMU.
External regulated4.75–5.25V -> J7 pin1 -> F2 -> D8 -> same CORE_5V_OR.
D1/D8 cathodes share CORE_5V_OR; diode OR prevents hard cross-feed but has reverse leakage. This is not a zero-leakage priority power mux. Neither rail powers accessories. External current-limited5V BEC required away from USB bench use. NO LiPo power input or onboard battery buck/BEC.
F405 U1 with inherited supply/VCAP/reset/boot/SWD support; active8MHz oscillatorY1, requires custom HSE bypass. ICM42688 U2 SPI1 with PC4 interrupt/PB15 CLKIN; W25Q128 U3 SPI3 single-SPI16MB flash. Driver and orientation tests pending.
Four motor3.3V signalsPB1/PB0/PB10/PB11 through100ohmR7–R10,100kohm boot pulldownsR11–R14, D3 ESD array and customJ3.
UART1 receiver andUART2 GPS through1kohm seriesR15–R18 andD4/J4. UART3/4 expansionR19–R22,D5/J5. UART6 expansionR23/R24,D6/J6. UART5 RXPD2 telemetryR25,D7/J7. Initial UART115200baud; higher rates qualify with actual cable. Noninverted3.3V serial only; no SBUS inverter or5V level shifter.
I2C1PB6/PB7 onJ6, single4.7kohm pullup pairR26/R27 to3V3; initial100kHz, total bus capacitance100k/10k dividerR28/R29 ->1kR32 ->PC1/C21(100nF)/D7. Nominal6S25.2V, screening bound30V; not characterized for real ESC surges beyond30V.
Current sensor J7 pin4 ->10k/10kR30/R31 ->1kR33 ->PC5/C22(100nF)/D7. External sensor voltage0–5V; no onboard shunt or amp calibration assumed.
Custom connector contract
All maps refer to schematic pin numbers; validate physical pin1 marking and cable orientation against future footprint/assembly. NOT stock cable compatible.
- J2:1=3V3 sense ONLY,2=GND,3=SWDIO,4=SWCLK,5=NRST,6=BOOT0.
- J3:1=M1,2=M2,3=M3,4=M4,5/6=GND.
- J4:1=TX1,2=RX1,3=GND,4=TX2,5=RX2,6=GND.
- J5:1=TX3,2=RX3,3=GND,4=TX4,5=RX4,6=GND.
- J6:1=TX6,2=RX6,3=GND,4=I2C1_SCL,5=I2C1_SDA,6=GND.
- J7:1=regulated5V INPUT,2=GND,3=VBAT SENSE ONLY,4=current0–5V,5=ESC3.3V telemetry RX,6=GND.
TX/RX labels are FC perspective. Cross-connect to peripheral RX/TX. No3V3 accessory power exposed. Independently powered peripherals must shareGND; do not drive any signal when FC is off. ESD arrays and series resistors do not provide DC overvoltage or powered-off isolation.
Power budget and operating envelope
Logic170mA allocation, IMU10mA allocation, aggregate180.16mA including two80uA IQ allowances. Fuses rated0.50A20C/0.34A60C,6V. Initial bench ambient<=40C and regulated current-limited supply; thermal and startup validation pending. USB starts low-current, must remain below100mA before authorization; request at least250mA before full-rate MCU/flash activity. Firmware power gating is not hardware-enforced. See core-power-budget.
Firmware contract
Custom target required. Pin resources documented against Betaflight config1e3f7782bfbc and MCU alternate-function evidence. Actual source clock mismatch is resolved by choosing active8MHz HSE-bypass architecture, not guessed crystal replacement; the patch/build is still undelivered. Source af0638839ac3 clears HSEBYP and SetSysClock starts HSE without setting bypass. Fork and patch before enable; measure8MHz/168MHz/48MHz. ReceiverUART1/GPSUART2 are custom defaults, unlike referenceUART6/UART4. ADC ratios11 and2 require measured calibration; reference current scale36 must not be reused.
Deliberately omitted features
OSD, barometer, wireless/Bluetooth/proprietary app support, camera control, LEDs, buzzer, servos, RSSI, switched auxiliary BECs and onboard5V/9V accessory BECs are omitted from approved first prototype scope, not silently promised. Original10pin harness map remains unavailable; independent custom headers replace that dependency. No55A ESC capability or OX32 compatibility claimed.
Release gates
Detailed schematic arrangement/visual-wire cleanup is blocked by absent mutation API; Functional Group organization is implemented using supported properties. Passive sense DC/AC/transient simulation passed bounded screening, not ADC/ESD qualification. AP2112 dynamic stability, effective MLCC values, power transition/leakage/inrush and thermal tests remain open. Footprint verification including STM32LQFP64, ESD array package, connector numbering, spacing and height required before layout. Custom firmware build, DFU, IMU clock/alignment and flash tests are not completed. Aircraft/battery transient protection must be characterized externally. No manufacture or flight approval follows from this checkpoint.