FC ma power protection, char motor signals, UART/I2C interfaces ane voltage/current sensing umeraya chhe—have 78 components ane 68 nets chhe. Hu final electrical check karu chhu; ESC project ni access haju fail thay chhe, etle tenu kaam complete thayu evu nahi kahu.
Electrical review ma floating-pin errors nathi; 12 ERC errors baki chhe, jena source-detection sambandhit karano document karya chhe.
Specification, firmware requirements ane bring-up plan update karya.
Haju project purn nathi: capacitor/resistor ratings ni qualification, USB VBUS detection ane power policy, custom firmware build/testing, 39 × 39mm PCB placement/routing baki chhe. FC ne regulated 5V joie—raw LiPo power input par na jodsho. ESC project ni access fail thai, etle tena power stages ke routing ma aa vakhat changes nathi karya; 55A rating verify nathi.
Execution tamara ACUs pura thai gaya etle rokayu; banne boards haju manufacturing ke flight mate ready nathi.
All active-scope external interfaces are now wired. Custom prototype firmware REQUIRED; no tested binary, patch or build delivered. Do not assume stock SPEEDYBEEF405V5 compatibility. Remove absent features and change UART defaults. Source evidence and ERC limits live in interface-and-firmware-gates.
Actual resources
Table
Function
MCU pins
Interface / implementation
Driven8MHz HSE
PH0;PH1NC
Y1 ->HSE_8MHZ; custom bypass startup
IMU SPI1
PA5SCK/PA6MISO/PA7MOSI/PA4CS
U2;PC4 interrupt;PB15 CLKIN
Flash SPI3
PB3SCK/PB4MISO/PB5MOSI/PC12CS
U3; release JTAG, retain SWD
USBFS
PA11DM/PA12DP
J1/D2; firmware self-powered behavior must account external5V
SWD
PA13/PA14
J2 pins3/4;NRSTpin5;BOOT0pin6
Motor1
PB1 TIM3_CH4 AF2
R7 100ohm ->J3pin1;100k pulldown
Motor2
PB0 TIM3_CH3 AF2
R8 ->J3pin2
Motor3
PB10 TIM2_CH3 AF1
R9 ->J3pin3
Motor4
PB11 TIM2_CH4 AF1
R10 ->J3pin4
UART1 receiver
PA9TX/PA10RX AF7
J4pins1/2;1k series
UART2 GPS
PA2TX/PA3RX AF7
J4pins4/5;1k series
UART3 expansion
PC10TX/PC11RX AF7
J5pins1/2
UART4 expansion
PA0TX/PA1RX AF8
J5pins4/5
UART6 expansion
PC6TX/PC7RX AF8
J6pins1/2
UART5ESC telemetry
PD2RX AF8
J7pin5;R25 1k; noUART5TX
I2C1
PB6SCL/PB7SDA AF4
J6pins4/5;4.7k pullups to3V3
VBAT ADC
PC1 ADC123_IN11
J7pin3;100k/10k plus1k/100nF; nominal ratio11
Current ADC
PC5 ADC12_IN15
J7pin4;10k/10k plus1k/100nF; nominal ratio2
J2 order1=3V3 sense ONLY,2GND,3SWDIO,4SWCLK,5NRST,6BOOT0. Never power the LDO output from debugger3V3. PB2BOOT1 is pulled low. BOOT0 may be externally strapped to3V3 for recovery; test ROM DFU clock behavior separately.
Chosen architecture: retainY1 active8MHz and PH1NC; custom startup must set RCC_CR_HSEBYP while HSE disabled before the HSE start, after SystemInit reset. Audit every recovery/clock-reset path. No stock binary guarantee. For unoverclockedF405 the read source computes8MHz ->pll_m4,pll_input2,pll_n168,pll_p2,pll_q7 giving168MHz core and48MHz USB. These are source-derived required values, NOT a tested implementation. Failure to become HSE/PLL ready must keep outputs inactive, not silently run flight control on a wrong timebase. Build and hardware verification remain gates.
Custom target differences
Use distinct board/target name. Reuse only mapped active resources from source; motor TIMER_PIN_MAP selections are(2,0),(2,0),(1,0),(1,1) for M1–M4. These mapping indices are not GPIO AF numbers; datasheet AFs are shown above. Verify DMA allocation and DShot implementation for chosen Betaflight revision. Initial DShot300 unidirectional; bidirectionalDShot and cable timing not established.
Set receiverUART1/GPSUART2 rather than referenceUART6/UART4; configure noninverted3.3V UART receiver protocol. No SBUS inverter supplied. UART1 is not Bluetooth/MSP by default. Disable OSD,barometer,wireless,PINIO,buzzer,LED,camera,RSSI,servo resources. NC pinsPC13/PC14/PC15/PC0/PC2/PC3/PB12/PB13/PB14/PC8/PC9/PA8/PA15/PB8/PB9 should not be initialized as stock outputs.
ADC configuration and calibration
Start ADC sample time480cycles, rate=10ms settling when enabling channels. PC1 filter157.721Hz;PC5filter265.258Hz passive simulation. Validate real sample loading and VDDA. Firmware voltage reconstruction uses measuredVDDA, nominalVBAT=11Vadc, external sensorV=2Vadc. Then apply measured sensor slope/offset to amperes; no onboard current shunt exists. Never reuse reference current scale36. Calibrate against known supplies and current reference at multiple points. Normal sense boundVBAT25.2V;30V is a screening ceiling, not a surge rating.
Startup and power discipline
GPIO CS high and motor outputs low before bus activity; retain SWD. USB-only preauthorization must stay below100mA (lowclock,flash/IMU idle); request>=250mA before168MHz logging. External5V mode permits bounded180.16mA core only, no accessory loads. There is no dedicatedUSBVBUS sense pin becausePA9 isUART1TX; inspect/configure USB device stack for no-VBUS-sense/self-powered operation and prevent attachment signaling without hostVBUS. This firmware gate is not resolved by diodeOR. Do not drive FC interface pins when FCoff; independently powered peripherals need sequencing/isolation offboard.
Read flash JEDEC and test program/erase/read. Read IMU WHO_AM_I, configure SPI and interrupt polarity explicitly. PB15CLKIN is inherited reference resource; timer frequency/mode must be validated before enabling external gyro clock. Physical alignment must follow actual future placement, not assumedCW270. Verify8MHz oscillator,clock trees,USB enumeration both orientations,DFU recovery,motor waveform and failsafe with props removed. No compiled code or flight qualification claimed.