Getting Started with Flux

Thought for 2 mins 16 sec
Thought for 8 sec
1/4 Verify FC ratings, USB detection and regulated-5V changes; C5/C6 qualification evidence still blocked.

Verify FC ratings, USB detection and regulated-5V changes; C5/C6 qualification evidence still blocked.

Recover ESC project access (blocked: saved UUID/link cannot be resolved).

Build and check safe bring-up firmware; full flight-firmware integration remains open.

Size and place FC PCB at 39 × 39mm after electrical gates; verify before routing.

Thought for 14 sec
Awaiting 1 task
"Flight Controller Readiness Review" completed.

flux

Aa vakhat actual FC changes ane firmware compilation karya chhe—project have 80 components ane 69 nets par chhe.
  • Ratings: 22 capacitors ane 36 resistors ni ratings configure/check kari; C16–C19 mate Murata 4.7µF, 16V, X7R, 0805 parts select karya. C5/C6 VCAP capacitors ni effective capacitance/ESR qualification haju baki chhe.
  • USB/power: PC0 par active-low USB VBUS detection umeru, PA9 UART signal preserve karyo. USB have data-only chhe—USB thi board power nahi thay. External regulated 5V jaruri chhe; raw LiPo power input par na jodsho.
  • Firmware: safe bring-up ELF/BIN/MAP ane source compile karya; mapping ane USB-detection logic na host tests pass thaya. Aa image motor outputs LOW rakhe chhe ane USB attach kartu nathi—aa working flight firmware nathi. Artifacts Firmware Build Results ma chhe.
Haju baki: full Betaflight integration, capacitor qualification, final electrical review findings, 39 × 39mm PCB sizing/placement/routing, ane hardware testing. Last full ERC check ma 10 errors documented hata; clean ERC claim nathi. ESC no saved project link access na thayo, etle ESC power stages/routing ma changes nathi karya ane 55A rating verify nathi; access issue mate Flux Support jaruri chhe.
Banne boards haju manufacturing ke flight mate ready nathi. Tamara ACUs pura thai gaya etle execution rokayu.

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Files

Schematic

Layout

3D View

Schematic is Auto-placed

The schematic has been arranged automatically. Flux can redraw it to be more readable, with components placed in related groups and wires drawn more legibly. This takes about 10-60 mins.

Electrical Completion Review
MLCC follow-up (2026-10-08)
C16–C19 now selected Murata GRM21BR71C475KE51L,4.7uF16V10%X7R0805. This supersedes their earlier2.2uF0603 guidance below. Typical bias-derived screen1.59uF supports prototype choice only; combined-condition guaranteed minimum remains open. C5/C6 MPN/bias/ESR selection blocked by pending datasheet indexing and lifecycle uncertainty; other16 capacitors remain generic. See mlcc-qualification-review for per-capacitor evidence, disposition and verification. No unconditional layout-ready declaration.
Scope disposition
  • COMPLETED: read saved schematic/docs; configured22 capacitors16V ceramic10% and36 resistors0603/0.1W/1%, R28 additionally50V; read-only sweep verified all properties.
  • COMPLETED: no source backfeed policy implemented by external regulated5V-only FC power, USBdata-only. RemovedD1/F1, deletedemptyUSB_VBUS_FUSED, renamedCORE_5V_OR->CORE_5V. ExistingF2/D8 protects regulatedinput; rawbattery sensing-only retained. USBalone no longer powers board.
  • COMPLETED: added gate-isolated VBUS presence detection Q1/R34/R35/R36;PC0 LOW=VBUSpresent. Existing PA9UART1TX and all motor/UART/I2C/ADC pins preserved. Custom firmware attach/detach still must be implemented; this electrical batch does not deliver firmware.
  • COMPLETED: power/ADC/sensor screening and passive analogDC/AC/transient simulation; specification/budget/firmware/bring-up/gates updated.
  • FAILED/BLOCKED: unconditional layout-ready or electricalrelease cannot be established until actualMLCC selection/bias/ESR, customfirmware and hardwarethermal/startup/transient/ESD tests. Detailed symbol arrangement mutation API absent; new detector has logicalnets and functionalgroup but visualwirecleanup is not completed.
  • UNATTEMPTED: validatedactiveLDO/MOSFETdynamicSPICE (no qualified models), PCB/layout/routing/export and firmwarebuild (outside assigned schematic scope).
Power and ratings rationale
Existing170mA logic allocation includes117mA worst listed MCU digitalrun,25mA flash,7mA oscillator,1.404mA I2C andmargin. Add0.33mA detector pullup inside margin; IMU10mA allowance plus two80uA IQ estimates =>180.16mA input allocation. MCU enabledADC analog adds1.6mA perADC and is covered by margin. External source>=250mA capability/currentlimited,4.75–5.25V only. F2 existing0.5Ahold screen and D8 existing1A40V comfortably above allocation; source remains responsible for overvoltage/transients. U4 conservative(5.25-3.3)*0.170=0.3315W;184C/W gives61.0C rise. U5 0.0195W/3.6C rise. AP2112 recommendedVIN2.5–6V and184C/W independently confirmed. Benchambient=3.9V underworstload because allowance not guaranteedtemperaturebound. Caps normalvoltage=1uF afterbias/temperature/tolerance; actualMPN notqualified. VCAP2.2uF lowESR requirement retained. No capacitorcurrentrating invented without rippledata. Resistor screen: highestDC lossR287.44mW at30V,vs100mWrating;voltageacrossR2827.27V,50Vworkingminimum specified. CC at5.25V evenentirevoltage across5.1k gives5.4mW.3.3V/4.7k pullup2.32mW,3.3V/10k1.09mW,3.3V/100k0.109mW. UART1k stucklow10.89mW/3.3mA; motor100ohm short would demand33mA (GPIOunsafe and109mW), so no sustainedshort allowance: interfacesCMOS3.3V only. External poweredoff signals prohibited; ESDarrays notDC translators/isolation.
VBUS circuit evidence
USBVBUS ->R34 10k ->Q1gate;R35 100k gate->GND. Q1sourceGND,drainPC0/R36 10k->3V3. Gate-node4.090909V at4.5VVBUS,4.08341V minimum1%corner. Q1 maximumgatevoltage20V; thresholdmax2.5V at250uA; RDSon4ohmmax atVGS4.5V/25C. Gate atlowVBUS isbelowRDS characterizationvoltage, so benchvalidate PC0logiclow/temperature rather thanclaim guaranteed4ohm. Gate insulation preventsDCUSB-to-core injection; commonGND means notgalvanicisolation. USBprotectorD2 remainsVBUSreferenced. PA9 is USART1TX andOTG_FS_VBUS. No directVBUS ties toMCU; customstack must disablePA9 sense and gateattachment fromPC0. StockROMDFU support unverified;SWD recoverycontract retained.
Simulation and verification
NativeSPICE fromactualsavedvalues R28=100k/R29=10k/R32=1k/C21=100nF and R30/R31=10k/R33=1k/C22=100nF: ADCVBAT30V->2.727273V nominal/2.77727V max1%corner; current5V->2.5V/2.525Vcorner. VBAT25.2V step final2.290909V. Cutoffs157.721Hz/265.258Hz; timeconstants1.00909ms/0.600ms,0.1%settling6.97056ms/4.14464ms afterstep,monotonic/noovershoot. ADCrange0–VREF+ verified. Models excludeADCsampling,ESDconduction,gatecapacitance,MOSFETbehavior andLDOstability. SafeDCscreen notwholeboardqualification. Read-onlynetinspection confirms CORE_5V onlyD8/U4/U5/C16/C18; USBVBUSonlyconnector/D2/R34;3V3_IMUincludesU5VOUT andsensorVDD/VDDIO; VCAPseparate;rawVBATonlyJ7/R28. Finalcounts80components/69nets afterempty-netcleanup. ERC04:22:43Z:10Errors/0Warnings:2IMUpowersourceinference and8USBexternalground/VBUSinference. No errorssuppressed. PriorCOREsourceinference findingsmayreturnafterrecalculation; verifyactualnet/sourcepath ratherthanaddingdummyflags. No reportedfloating/short/driverconflict remains. AcleanERCclaim is expresslynotmade.

  • MLCC follow-up (2026-10-08)

  • Scope disposition

  • Power and ratings rationale

  • VBUS circuit evidence

  • Simulation and verification