Getting Started with Flux

Thought for 2 mins 16 sec
Thought for 8 sec
1/4 Verify FC ratings, USB detection and regulated-5V changes; C5/C6 qualification evidence still blocked.

Verify FC ratings, USB detection and regulated-5V changes; C5/C6 qualification evidence still blocked.

Recover ESC project access (blocked: saved UUID/link cannot be resolved).

Build and check safe bring-up firmware; full flight-firmware integration remains open.

Size and place FC PCB at 39 × 39mm after electrical gates; verify before routing.

Thought for 14 sec
Awaiting 1 task
"Flight Controller Readiness Review" completed.

flux

Aa vakhat actual FC changes ane firmware compilation karya chhe—project have 80 components ane 69 nets par chhe.
  • Ratings: 22 capacitors ane 36 resistors ni ratings configure/check kari; C16–C19 mate Murata 4.7µF, 16V, X7R, 0805 parts select karya. C5/C6 VCAP capacitors ni effective capacitance/ESR qualification haju baki chhe.
  • USB/power: PC0 par active-low USB VBUS detection umeru, PA9 UART signal preserve karyo. USB have data-only chhe—USB thi board power nahi thay. External regulated 5V jaruri chhe; raw LiPo power input par na jodsho.
  • Firmware: safe bring-up ELF/BIN/MAP ane source compile karya; mapping ane USB-detection logic na host tests pass thaya. Aa image motor outputs LOW rakhe chhe ane USB attach kartu nathi—aa working flight firmware nathi. Artifacts Firmware Build Results ma chhe.
Haju baki: full Betaflight integration, capacitor qualification, final electrical review findings, 39 × 39mm PCB sizing/placement/routing, ane hardware testing. Last full ERC check ma 10 errors documented hata; clean ERC claim nathi. ESC no saved project link access na thayo, etle ESC power stages/routing ma changes nathi karya ane 55A rating verify nathi; access issue mate Flux Support jaruri chhe.
Banne boards haju manufacturing ke flight mate ready nathi. Tamara ACUs pura thai gaya etle execution rokayu.

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Files

Schematic

Layout

3D View

Schematic is Auto-placed

The schematic has been arranged automatically. Flux can redraw it to be more readable, with components placed in related groups and wires drawn more legibly. This takes about 10-60 mins.

Core Power Budget
Authoritative revision — external5V only
USB power branch D1/F1 removed; no source OR/changeover now exists. External4.75–5.25V -> F2 -> D8 -> CORE_5V remains. USB data-only detection draws approximately41–48uA from host through R34/R35, not the180mA core. R36 adds0.33mA to the existing170mA logic allocation (absorbed in margin). Aggregate allocation remains180.16mA; use at least250mA current capability externally, with adjustable bench current limit. No accessory loads. Thermal screen unchanged: U4 worst conservative Pd0.3315W and rise61C, U5 Pd0.0195W. AP2112 SOT25 thetaJA184C/W and recommendedVIN2.5–6V are independently rechecked. This is a bench=1uF at5.25V and C17/C19>=1uF at3.3V required. No specific MLCC bias/ESR curve qualified. Require X7R purchasing specification. The previous USB authorization/core-changeover discussion below is historical and does not apply to current data-only USB architecture.
Historical budget below (superseded power policy)
Active design —2026-10-08
USB or external regulated4.75–5.25V input through individual0.5A PTCs and SS14 diodeOR to CORE_5V_OR. NoLiPo supply/no onboardbuck/noaccessorypoweroutputs. Peripherals externallypowered. This supersedes inheritedUSB-only150mA allocation.
Loads and bounds

Table

RailLoadEvidence / allocation
3V3STM32F40587mA typical ART/peripherals;109mA maximum listed at105C/3.6V;117mA worst listed withoutART.
3V3Flash25mA maximumprogram/erase.
3V3Y1ASE8MHz7mAmaximum for0.5–20MHz;3.135–3.465Vsupply.
3V3I2Cpullups2*3.3/4700=1.404mA ifbothheldlow (calculated)
3V3CS/boot/bias/ESD/IOIncludedinremainingmargin;motor100kloads4*3.3/100k=0.132mA; externalinputs assumedCMOS noDCloads
3V3_IMUICM426880.88mAtypicallow-noise1.8V/25C,not3.3Vmax;10mAengineeringallocation.
Logicallocation170mA includes149mA MCU+flash+oscillator,1.404mApullups and~19.6mAmargin. IMUallocation10mA. LDOinput currentapproximatelyequalsoutputload; two80uA IQ allowances yield180.16mA sourcebound. AP2112IQ80uAmax ischaracterizedVIN4.3V/no-load,notclaimedas all-condition maximum. No external3V3load permitted. GPIOdrivers are3.3Vsignals notpoweroutputs.
Power-path sizing
F1/F2 0603L050YR:0.50Ahold20C,0.34Ahold60C,6Vmax,R1max0.680ohm. 1.5*180.16mA=270.24mA=3.9V atfullallocation. USBcablesmaydroopfurther;brownout behaviorrequiresbenchtest. Worst screeningignoringdiodebenefit:U4P=(5.25-3.3)*0.170=0.3315W;U5P=0.0195W. SOT25thetaJA184C/Wnoheatsink predictsU4rise61.0C/U5rise3.6C. Initialambient=datasheet1uFapplicationcapacitance; inheritedC16–C19nominal2.2uFareonlyallocationuntilactualMLCCbiascurve/ESRarechecked.
USB and protection limits
USBpreauthorization=250mAbeforefull168MHzlogging.0.5APTCdoesnotenforceauthorization. NoaccessoryUSBloads. Transition,inrush,LDOstability,reverse-dischargeandpoweredoffsignalbehaviornotmodeled. PowerdynamicSPICEnotclaimedbecausevalidatedAP2112andSS14modelswerenotobtained. AnalogverificationislimitedtoactualpassiveADCnetworks. NoEM/thermalmanufacturingapproval.

  • Authoritative revision — external5V only

  • Historical budget below (superseded power policy)

  • Active design —2026-10-08

  • Loads and bounds

  • Power-path sizing

  • Headroom and thermal screening

  • USB and protection limits