The connectivity comparison confirms that all 49 nets still connect the same pins. The readability check found more work in the op-amp stages and electrode-jack wiring, which I’m correcting now.
The analog stages now have drawn signal paths, but a wire-placement bug on flipped symbols is blocking part of the USB drawing. I’ll leave the affected connections labeled and finish the independent label fixes; the bug needs Contact Support.
I arranged all 78 components into eight functional blocks and added local wires and net labels. All 49 nets retain exactly the same pin connections; no electrical connections changed.
The drawing is not fully clean: wire crossings and label crowding remain, and a flipped-symbol wire-placement bug blocks the shared USB power wire. That bug needs Contact Support; the remaining drafting cleanup is still open.
Revision 2026-10-28. This is the self-contained reproduction reference for the implemented AD8232 / MCP6002 circuit, capture commit 07d2baa4: 71 components and 44 electrically connected nets. The schematic summary also retains eight empty names; these are not electrical nets and are deliberately omitted. Read-only component-property and pin-membership inspection confirms the following inventory. The current ERC read reports 0 errors and 1 warning, the existing D4 pin-type limitation. No PCB manufacture, complete analog validation, or human-use approval follows from ERC.
Use an electrode simulator only. No onboard isolation exists. External isolated USB power and data, shield, SWD, instruments and every alternate conductive/capacitive path require qualified whole-system isolation, leakage and fault verification before any human connection. J1 sleeve is a driven electrode, never board ground. There is no GPIO plug detector.
2. Complete live component inventory
Endpoint pairs in passive tables are electrically unordered unless pin numbers are explicitly given. All 26 ordinary resistors are 0402; generic entries are design specifications, not qualified exact MPNs. The generic resistor power property is 0.063 W; actual procurement, derating and pulse capability remain gates. R4/R5 have no meaningful percentage tolerance: their fitted absolute resistance/current rating is TBD.
Resistors — 26
Table
Ref
Value; tolerance
Endpoints
Procurement / function
R1
10 Ω; 1%
3V3 — 3V3A
Analog rail filter; inrush/short pulse qualification open
R2
10 kΩ; 1%
BOOT0 — GND
Boot default low
R3
10 kΩ; 1%
5V_USB — USB_VBUS_SENSE
VBUS divider upper
R4
0 Ω; absolute R TBD
USB_DP_CONN — USB_D+
USB series link
R5
0 Ω; absolute R TBD
USB_DM_CONN — USB_D-
USB series link
R6
180 kΩ; 1%
EMG_P_JACK — EMG_P_PROT
RC0402FR-07180KL, body-facing limiter
R7
180 kΩ; 1%
EMG_P_PROT — INA_INP
Same exact MPN, AFE-facing limiter
R8
180 kΩ; 1%
EMG_N_JACK — EMG_N_PROT
Same exact MPN, body-facing limiter
R9
180 kΩ; 1%
EMG_N_PROT — INA_INN
Same exact MPN, AFE-facing limiter
R10
10 MΩ; 1%
INA_INP — VMID
Bias return
R11
10 MΩ; 1%
INA_INN — VMID
Bias return
R14
100 kΩ; 0.1%
3V3A — VMID_DIV
REFIN divider upper
R15
100 kΩ; 0.1%
VMID_DIV — GND
REFIN divider lower
R16
8.06 MΩ; 1%
INA_OUT — HPSENSE
Servo; leakage-sensitive
R17
402 kΩ; 0.1%
GAIN_FB — GAIN_OUT
Postamp feedback, always present
R19
100 kΩ; 0.1%
GAIN_FB — GAIN_SEL
Lower gain leg, dead-ended with J4 open
R20
287 kΩ; 1%
GAIN_OUT — LP1_A
LP1 first series resistor
R21
287 kΩ; 1%
LP1_A — LP1_B
LP1 second series resistor
R22
549 kΩ; 1%
LP1_OUT — LP2_A
LP2 first series resistor
R23
549 kΩ; 1%
LP2_A — LP2_B
LP2 second series resistor
R24
100 Ω; 1%
LP2_OUT — ADC_EMG
ADC isolation
R27
200 kΩ; 1%
RLD_OUT — RLD_MID
RC0402FR-07200KL, AFE-facing limiter
R28
200 kΩ; 1%
RLD_MID — RLD_JACK
Same exact MPN, body-facing limiter
R29
5.1 kΩ; 1%
USB_CC1 — GND
Independent USB-C Rd
R30
5.1 kΩ; 1%
USB_CC2 — GND
Independent USB-C Rd
R31
20 kΩ; 1%
USB_VBUS_SENSE — GND
VBUS divider lower
The exact 180/200 kΩ Yageo parts are 1/16 W at 70°C, 50 V continuous, 100 V specified overload, 100 ppm/°C. These ratings do not establish ESD/pulse survival.
Capacitors — 30
Packages below are live design assignments. X5R/X7R effective capacitance under bias is not included in nameplate tolerance. C22 has no explicit live dielectric property; treat its dielectric/effective-C selection as unqualified rather than inventing one.
Table
Ref
Value; tolerance; voltage
Dielectric; package
Endpoints
C1
4.7 µF; 20%; 16 V
X5R; 0603
5V_USB — GND
C2
1 µF; 10%; 16 V
X7R; 0402
5V_USB — GND
C3
1 µF; 10%; 10 V
X7R; 0402
3V3 — GND
C4
10 µF; 20%; 10 V
X5R; 0603
3V3 — GND
C5
10 µF; 20%; 10 V
X5R; 0603
3V3A — GND
C6
100 nF; 10%; 16 V
X7R; 0402
3V3A — GND
C7
100 nF; 10%; 16 V
X7R; 0402
3V3 — GND, U1 pin24
C8
100 nF; 10%; 16 V
X7R; 0402
3V3 — GND, U1 pin36
C9
100 nF; 10%; 16 V
X7R; 0402
3V3 — GND, U1 pin48
C10
4.7 µF; 20%; 10 V
X7R; 0603
3V3 — GND, MCU bulk
C11
4.7 µF; 20%; 6.3 V
X5R; 0603
VCAP1 — GND
C12
1 µF; 10%; 10 V
X7R; 0402
3V3A — GND, U1 VDDA
C13
100 nF; 10%; 16 V
X7R; 0402
3V3A — GND, U1 VDDA
C14
100 nF; 10%; 16 V
X7R; 0402
3V3 — GND, U1 VBAT
C15
100 nF; 10%; 16 V
X7R; 0402
MCU_NRST — GND
C16
18 pF; 5%; 50 V
C0G; 0402
HSE_IN — GND
C17
18 pF; 5%; 50 V
C0G; 0402
HSE_OUT — GND
C18
47 pF; 5%; 50 V
C0G; 0402
INA_INP — INA_INN
C19
10 pF; 2%; 50 V
C0G; 0402
INA_INP — GND
C20
10 pF; 2%; 50 V
C0G; 0402
INA_INN — GND
C21
100 nF; 10%; 16 V
X7R; 0402
3V3A — GND, U3 bypass
C22
1 µF; 20%; 10 V
Dielectric qualification open; 0402
VMID_DIV — GND
C23
100 nF; 5%; 100 V
C0G; 1206
Pin1 HPDRIVE — pin2 HPSENSE
C24
1.2 nF; 5%; 50 V
C0G; 0402
LP1_A — LP1_OUT, feedback
C25
1 nF; 5%; 50 V
C0G; 0402
LP1_B — GND
C26
1.5 nF; 5%; 50 V
C0G; 0402
LP2_A — LP2_OUT, feedback
C27
220 pF; 5%; 50 V
C0G; 0402
LP2_B — GND
C28
1 nF; 5%; 50 V
C0G; 0402
ADC_EMG — GND
C29
100 nF; 10%; 16 V
X7R; 0402
3V3A — GND, U4 bypass
C30
10 nF; 5%; 50 V
C0G; 0402
Pin1 RLDFB — pin2 RLD_OUT
C23 is exact GRM31C5C2A104JA01L, not a generic capacitor. Its 100 nF / C0G / 5% / 100 V specifications and 1206 dimensions are sourced. IR product >500 Ω·F implies >5 GΩ under the manufacturer's room-temperature test conditions; this is not a hot leakage limit.
Remaining components — 15
Tolerance is not applicable unless stated in the device datasheet; no invented global percentage is assigned.
Table
Ref
Exact part; package
Connections / role
U1
STM32F401CEU6; UFQFPN48 + EP
Recorder and ADC; full map below
U2
TPS7A2033PDBVR; SOT23-5
3.3 V regulator; full map below
U3
AD8232ACPZ-RL; LFCSP20 + EP
INA, servo, reference, postamp, RLD; full map below
1 GAIN_SEL; 2 VMID; open low gain, shunted high gain
3. All IC pins and reference fanout
U3 AD8232
Table
Pin
Function
Live net
1
HPDRIVE
HPDRIVE
2
+IN
INA_INP
3
−IN
INA_INN
4
RLDFB
RLDFB
5
RLD
RLD_OUT
6
SW
VMID
7
OPAMP+
INA_OUT
8
REFOUT
VMID
9
OPAMP−
GAIN_FB
10
OUT
GAIN_OUT
11/12
LOD− / LOD+
NC
13
SDN, active low
3V3A, enabled
14
AC/DC
GND, DC lead-off mode
15
FR
GND, fast restore disabled
16
GND
GND
17
+VS
3V3A
18
REFIN
VMID_DIV
19
IAOUT
INA_OUT
20
HPSENSE
HPSENSE
21 / EP
Exposed pad
GND
Pin map and EP connection are manufacturer based. SW→VMID is an accepted engineering interpretation of the disabled switch with FR low, not a verbatim manufacturer instruction for an unused pin. AC/DC low does not fully disable lead-off; its outputs are unused.
VMID fanout is precisely U3 REFOUT8, U3 SW6, R10 lower, R11 lower and J4 pin2. J4 connects R19 to VMID only when shunted. C22 is on REFIN/VMID_DIV, not REFOUT. No direct REFOUT bypass capacitor is fitted. REFIN sees R14/R15 100 kΩ each and C22 1 µF, nominal 50 ms. Divider endpoints are 0.4995–0.5005 of 3V3A. REFOUT noise, output impedance, loading, startup and capacitance stability must be validated; a typical short-circuit current is not a continuous-load rating.
U4 MCP6002
Pins 1 OUTA and 2 −INA are LP1_OUT; pin 3 +INA is LP1_B; pin 4 VSS is GND; pin 5 +INB is LP2_B; pins 6 −INB and 7 OUTB are LP2_OUT; pin 8 VDD is 3V3A.
U2 TPS7A2033
Pin 1 IN and pin 3 EN are 5V_USB; pin 2 is GND; pin 4 is NC; pin 5 OUT is 3V3. Input C1/C2 and output C3/C4 form the power boundary. R1 then feeds the analog rail, U1 VDDA/VREF+, U3 and U4; all MCU VDD/VBAT pins stay on 3V3.
U1 STM32F401CEU6 — complete physical map
Table
Pin(s)
Function / net
1
VBAT → 3V3
2/3/4
PC13 / PC14 / PC15 → NC
5/6
PH0 / PH1 → HSE_IN / HSE_OUT
7
NRST → MCU_NRST
8
VSSA/VREF− → GND
9
VDDA/VREF+ → 3V3A
10
PA0 / ADC1_IN0 → ADC_EMG
11–17
PA1–PA7 → NC
18/19/20/21
PB0 / PB1 / PB2 / PB10 → NC
22
VCAP1 → VCAP1 / C11 only
23/24
VSS / VDD → GND / 3V3
25–28
PB12–PB15 → NC
29
PA8 → NC
30
PA9 → USB_VBUS_SENSE
31
PA10 → NC
32/33
PA11 / PA12 → USB_D− / USB_D+
34
PA13 → SWDIO
35/36
VSS / VDD → GND / 3V3
37
PA14 → SWCLK
38
PA15 → NC
39–43
PB3–PB7 → NC
44
BOOT0 → BOOT0 / R2
45/46
PB8 / PB9 → NC
47/48
VSS / VDD → GND / 3V3
49 / EP
GND
USB-C J2: A1/A12/B1/B12 GND; A4/A9/B4/B9 VBUS_CONN; A5 USB_CC1; B5 USB_CC2; A6/B6 USB_DP_CONN; A7/B7 USB_DM_CONN; A8/B8 NC. Shell/tabs are board GND and therefore part of the external isolation review. R29/R30 are separate Rd resistors, no PD. Digital pins, USB PHY, crystal, LDO startup/inrush and switched ADC are not simulated by the signal macro. Firmware remains requirements only.
4. Reproducible model and provenance
Use simulator ground as isolated board GND, not earth. Differential jack AC stimulus is ±0.5 V around VMID to obtain 1 V differential normalization; these normalized AC amplitudes are not realizable signal swings. Use zero differential DC for AC, 3V3A=3.2 V and VMID=1.6 V as explicit headroom-screen assumptions. Signal contact impedance is zero in the nominal signal run; electrode/contact effects are separate sensitivity cases.
Model the actual input ladder with two 180 kΩ per leg, clamp-midpoint capacitance assumed 2 pF, 10 MΩ bias, 10 pF common-mode capacitors and 47 pF differential capacitor. Clamp nonlinearity/leakage/temperature are excluded. AD8232 differential INA gain is fixed 100. The manufacturer servo equation is fc = 100/(2πR16C23) = 19.7463 Hz; the physical RC product is 0.806 s, while the effective small-signal HP time constant is 8.06 ms.
A reproducible behavioral, not vendor, servo is raw=100(vINP−vINN), dx/dt=(raw−x)/8.06 ms, IAOUT=VMID+raw−x. This preserves the effective transfer; it does not model actual HPSENSE/HPDRIVE voltage, finite servo range, clamps, fast restore, saturation or nonlinear recovery. The numerical cancellation state can reach about ±29 V for ±300 mV at the jack; that is an obvious model limitation, not internal device headroom.
Postamp is VMID+Gpost(INA_OUT−VMID) with Gpost=1 open / 5.02 closed and an assumed closed-loop pole at 100 kHz/Gpost, based on typical postamp GBW. R17 remains in feedback with J4 open, R19 is dead-ended. Closed ratio tolerance 0.1% gives 5.01197–5.02805. AD8232's headline 2 kHz INA bandwidth is not an extra hidden pole in the principal run; a vendor or measured model must establish its actual effect. ±300 mV offset handling is settled DC capability, not instantaneous artifact headroom; gain error can reach 3.5% under cited conditions.
Each MCP6002 follower uses unity closed-loop K(s)=1/(1+s/(2π·1 MHz)), 6 pF from noninverting input to GND and 3 pF from that input to output. These are typical GBW/capacitance approximations, not a semiconductor model. The 3 pF is bootstrapped, not simply added to ground capacitance. Typical unity phase margin at the stated 60 pF test load does not prove this Sallen–Key/ADC network stable.
Ideal Sallen–Key section: H=1/[1+s·Cg(Ra+Rb)+s²RaRbCfCg]; f0=1/(2π√(RaRbCfCg)), Q=√(RaRbCfCg)/[Cg(Ra+Rb)]. LP1 is 506.23 Hz/Q0.5477, LP2 504.65 Hz/Q1.3056, low Q first. For finite K/Cin, nodal equations are (ga+gb+sCf)A−gbB−sCfY=gaVin, −gbA+[gb+s(Cg+Ccm+Cdiff)]B−sCdiffY=0, Y=K·B, where ga=1/Ra, gb=1/Rb. These equations also define source-specific noise transfer. ADC interface is the actual 100 Ω / 1 nF continuous-time RC only; no switched ADC model or aperture benefit is invented.
5. Executed native AC results
Native ngspice AC, DC operating point and linear transient were executed separately from analytical calculations. AC uses 400 and 800 points/decade from 1 Hz to 1 MHz, plus an exact-frequency 1 Hz-grid check. Outputs settle near 1.6 V at zero differential DC.
Table
Metric
J4 open
J4 closed
ADC gain at 20 Hz
68.69158
344.8316
ADC gain at 100 Hz
94.82377
476.0096
ADC gain at 500 Hz
67.75089
340.0066
Peak gain V/V
96.58724
484.8338
Peak-relative −3.000 dB edges Hz
19.8167–497.715
19.8139–497.658
Exact half-power −3.01030 dB edges Hz
19.7696–498.011
19.7669–497.954
Attenuation at 4 kHz versus 100 Hz
74.6568 dB
74.8214 dB
Attenuation at 7.5 kHz versus 100 Hz
99.8257 dB
100.377 dB
Attenuation at 8.02 kHz versus 100 Hz
102.600 dB
103.224 dB
Use consistent edge conventions. Native peak-location reports differ by roughly one grid interval (about 241.3 versus 240.6 Hz); no precisely optimized peak frequency is claimed. 400→800 points/decade changed edges ≤0.003 Hz / 0.00061%; this is sampling agreement, not proof of nonlinear convergence.
Table
Node maximum V/V
Open
Closed
INA_OUT
96.09211
96.09211
GAIN_OUT
96.09169
482.3304
LP1_A
93.78921
470.8144
LP1_OUT
92.25580
463.1194
LP2_A
98.70065
495.4263
LP2_OUT / ADC
96.58724
484.8338
Check internal nodes as well as ADC. Assuming ±1.5 V useful output excursion on a 3.2 V rail, 12 mVpk open / 2.4 mVpk closed produces about 1.16 V ADC amplitude, about 1.20 V with +3.5% gain error: capacity/demand≈1.25 before offsets/reference/other errors. This is a Warning-level provisional screen, not a guaranteed input range. Output swing, common-mode range and electrode spectrum/crest factor must be tested. Rapid offsets can overload the fixed G100 stage in either jumper state.
6. Executed DC and transient demand checks
DC sweep differential jack −300/0/+300 mV gives IAOUT≈1.600000 V and ADC≈1.599996 V in the ideal cancellation model. Numerical x is −28.9575/0/+28.9575 V. These results cannot validate real electrode-offset range. Adding +4.5 mV to each MCP follower gives ADC≈1.608996 V, approximately +9 mV. The manufacturer's ±4.5 mV offset condition is 25°C and VCM=VSS; this is not a guaranteed midrail/full-temperature board bound.
Transient stimulus: a differential pulse with 1 µs rise at 20 ms, 100 ms hold and return at 120 ms; record 200 ms. Outputs are unlimited and linear, without a clipping/recovery model. The 1/10 mV results are exact linear scaling of the executed 100 mV run, not separate nonlinear runs. Peak excursions above baseline:
Table
Jack step
INA_OUT both states
ADC open
ADC closed
1 mV
0.094196 V
0.097408 V
0.488964 V
10 mV
0.941960 V
0.974076 V
4.889641 V
100 mV
9.419600 V
9.740758 V
48.896410 V
Total time outside the assumed ±1.5 V demand screen, including both edges: at 1 mV, zero everywhere; at 10 mV, zero at INA/open ADC and 19.0800 ms at closed ADC; at 100 mV, 30.0725 ms at INA, 30.5194 ms at open ADC and 56.9944 ms at closed ADC. Closed-state GAIN_OUT additionally violates the screen for 18.9452 ms at 10 mV. These are not physical recovery/discard times. Refinement from 10 to 5 µs maximum timestep changed positive peaks ≤0.0028%, either-polarity extrema <0.0037% and durations ≤8.1 µs. At 199.999 ms after the 100 mV pulse, ADC is 1.599470 / 1.597356 V; finite-record samples are not fully settled DC.
Downstream DC offsets are not removed by the input high-pass. Typical MCP bias of 1.1 nA at 125°C can produce 0.63 / 1.21 mV through the 574 kΩ / 1.098 MΩ DC source resistances; typical drift is not a maximum. Board leakage of 1 nA through 549 kΩ gives 0.549 mV. Measure baseline/temperature; digital subtraction cannot restore clipped headroom.
7. Tolerance and parasitic sensitivity
Accepted design tolerances: LP resistors 1%, LP capacitors 5%, servo resistor 1% / capacitor 5%, gain resistors 0.1%. Servo endpoint fc is 18.6198–20.9955 Hz. A deterministic set of 512 cases combines all 256 LP passive endpoints with two worst-product HP endpoints, nominal input network and ideal followers: low edge 17.78–23.99 Hz, high edge 476.79–537.65 Hz, peak 93.91–102.79 V/V. This is not Monte Carlo, yield, or proof of every continuous interior extremum. There is no newly imposed exact 500 Hz amplitude mask.
The finite MCP model gives a nominal upper half-power edge of about 498 Hz. Assumed 10 pF total common-mode input/board capacitance gives about 492.8 Hz; assumed 20 pF with 300 kHz GBW gives about 480.2 Hz. These stress inputs are not guaranteed active-device limits. LP2's 220 pF makes even 6 pF relevant. Keep LP2_B compact and clean. Analytical 12,000/24,000-point grids agree in peaks <0.001%, edges <0.11% and earlier integrated partial noise within 0.011%; native AC and finite-Cin calculation agree far better than 2% at quoted nominal points.
8. Source-specific partial noise and SNR
Use 300 K and one-sided Johnson PSD 4kTR; integrate actual output PSD from 20 to 500 Hz, then divide RMS by jack-to-ADC gain at 100 Hz. This is a 100 Hz-equivalent input reference, not a claim of flat gain over the band. Clamp/electrode excess noise, input and servo current noise, AD 1/f spectrum, servo R16 transfer, internal postamp voltage/current noise, REFOUT/RLD/supply correlations and actual ADC noise are missing, not zero. AD 100 nV/√Hz and MCP 28 nV/√Hz are typical 1 kHz figures extrapolated flat for this partial calculation.
Inject each resistor as an independent parallel current source with PSD 4kT/R at its actual endpoints; solve the nodal equations above. For each follower, inject an input-referred voltage source in Y=K(B+en) so the actual noise gain is included. R17/R19 thermal sources use their real feedback noise gains and the modeled postamp pole. For divider thermal noise only, assume an ideal coherent REFOUT buffer: 50 kΩ Thevenin filtered by C22, common baseline propagated once through the LP chain. That small divider result does not include internal reference noise and is never copied into several independent RSS sources.
Table
Source; equivalent µVrms at jack /100 Hz
Open
Closed
Four 180 kΩ limiters
2.30573
2.30554
Two 10 MΩ bias returns
0.43748
0.43745
AD input flat 100 nV assumption
2.19163
2.19145
R20
0.01537
0.00306
R21
0.01794
0.00357
R22
0.02668
0.00531
R23
0.05165
0.01029
MCP channel A flat 28 nV assumption
0.01110
0.00221
MCP channel B flat 28 nV assumption
0.01771
0.00353
R17
0.01818
0.00362
R19
0, open circuit
0.00726
R24
0.00030
0.00006
REFIN divider thermal, ideal reference buffer
0.00021
0.00004
Partial RSS
3.21181
3.21085
Partial ADC output RMS
304.56 µV
1528.40 µV
The updated finite-Cin result is slightly different from an ideal-follower calculation; use this table consistently. Numerical integration from 2000 to 4000 linear samples changes RSS <0.000013%; ADC gains from the nodal model differ from native values by <0.001%. Precision shown permits reproduction, not production prediction.
Quantization separate from measured ENOB
At assumed VREF = 3.2 V and 12 bits: LSB = 781.25 µV, ideal uniform full-Nyquist quantization RMS = 225.53 µV. At 8 kS/s, the ideal white 20–500 Hz contribution is 78.125 µV at ADC, equivalent to 0.82389 / 0.16412 µV at the jack. Actual converter INL/DNL, reference noise, aperture, code-dependent noise and ENOB are not measured by this arithmetic.
For a 100 Hz sine with 10/100/1000 µVrms differential at the jack and crest factor √2, integrated 20–500 Hz partial analog noise plus ideal quantization yields SNR 9.59/29.59/49.59 dB open and 9.86/29.86/49.86 dB closed. These are illustrative partial-budget SNRs, not complete-board guarantees; another spectrum/crest factor requires integrating its output signal and checking every node. At 1000 µVrms, the closed-state ADC signal is about 0.476 Vrms / 0.673 Vpk, below the provisional headroom screen; artifacts can still overload it.
Aliasing is source-specific
Input-signal attenuation at 4/7.5/8.02 kHz in §5 must not be used for noise generated after the filters. Separately fold the listed downstream white approximations through their own transfer functions into 20–500 Hz at 8 kS/s, ideal point sampling, no aperture credit: sum positive-frequency bands [kfs−500,kfs−20] and [kfs+20,kfs+500], k≥1. Truncation at 400/800/1600 images, to 3.2/6.4/12.8 MHz, gives extra ADC RMS 9.5209/9.6140/9.6290 µV, final change 0.156%. Final equivalent input is about 0.1015 µV open / 0.02023 µV closed, dominated by final MCP modeled voltage noise. This extrapolates beyond the part's characterized headline frequency and is not a measured RF-noise model. R24's remaining ideal white tail and all omitted device/ADC noise remain limitations. The folded contribution scarcely changes the rounded SNR examples but cannot be called zero. Do not infer a 12-bit alias guarantee.
9. RLD return ratio — bounded bench starting point
C30 = 10 nF, C0G, 5%, between RLD_OUT and RLDFB. The manufacturer ideal controller uses internal 150 kΩ, A=1/(s·150 kΩ·C30); internal resistor accuracy and active poles are unqualified.
Reproduce a nine-node plant: body; three separate contact/cable nodes; three clamp midpoints; two AFE inputs. Driven branch: 200 kΩ + 200 kΩ. Signal branches: 180 kΩ + 180 kΩ, each with 10 MΩ to AC-ground VMID, 10 pF to board GND and 47 pF differential. Each midpoint has assumed 2 pF. Each cable independently has 100/200/500 pF to isolated board GND, all 27 combinations. Contact triples (reference,+,−), Ω: (5k,5k,5k), (50k,100k,200k), (200k,50k,1M), (1M,200k,50k). Body return to isolated GND is 0/50/200 pF in parallel with 10/100 MΩ. Total: 648 deterministic cases. Contacts are resistive; dispersive electrodes/open leads are not covered.
Drive 1 V at RLD_OUT; calculate P=average(INA_INP,INA_INN)/RLD_OUT, L=P/(s·150k·C30), characteristic 1+L=0. Evaluate every unity crossing with unwrapped phase. At 10 nF: crossover 63.79–94.35 Hz, minimum PM 55.33°, 60 Hz |L| 0.64–3.95 dB and sensitivity improvement 20log10|1+L| of 0.44–5.23 dB. This is weak/variable mains suppression, not whole-system CMRR. With C30 ±5% and an explicitly assumed 1 kHz active pole, minimum PM is 50.19°; worst 60 Hz improvement can become −0.26 dB. Refinement from 2000 to 4000 log samples over 0.1 Hz–100 kHz agrees in PM <0.0001° and crossing <0.001%.
Body-to-earth capacitance is not silently board-ground capacitance: a real isolated system needs the measured isolation/board-to-earth/instrument return network. Nominal 55.33°/45° screen = 1.23; stressed 50.19°/45° = 1.12: Warning, not robust sign-off. A 60° target is not met. Test real loop gain/step, open/reconnect, cable/contact bounds and saturation before release. No added lead-lag network is assumed.
10. ADC, power and passive screens
ADC assumptions: 12 bits, 8 kS/s, ADCCLK = 21 MHz, 480 acquisition cycles = 22.857 µs. Sourced CADC is typical 4 / maximum 7 pF and RADC maximum 6 kΩ under table conditions. Ideal full 3.2 V charge sharing with the 1 nF reservoir causes about a 22.24 mV step; 42 ns internal RC and 100 ns external RC alone are not a complete settling/stability proof. Target residual is <0.25 LSB, about 195 µV, by acquisition end for both mux-history extremes without sustained ringing. The 1 nF behind 100 Ω is outside the 60 pF condition of MCP's headline phase margin.
Analog quiescent illustration: AD about 0.170 mA typical, MCP dual 0.200 mA typical and divider 0.0165 mA at 3.3 V: total 0.3865 mA before MCU VDDA, dynamic and electrode loads. MCP dual maximum 0.340 mA is conditional at 25°C / 5.5 V / IO = 0, not an all-temperature board maximum. The AD headline is a conditional typical planning input; refreshed extraction did not machine-verify a 230 µA maximum, so no guaranteed AD maximum is used here.
Illustrative MCU allowance: 25 mA total including 2 mA VDDA, plus 2.5 mA miscellaneous and 0.3865 mA analog IC/divider, gives 27.89 mA. These are budget assumptions, not measured or guaranteed MCU maxima. Analog R1 current of 2.3865 mA gives 24.10 mV drop and 57.5 µW at R1 +1%; a conservative 5 mA analog allocation gives 50.5 mV / 0.2525 mW. Use measured analog load, not ideal 3.3 V, for headroom/reference work. Check the retained 60 mA envelope over firmware/USB/temperature.
U2 recommended capacity 300 mA versus the 60 mA envelope gives ratio 5.0; maximum DBV dropout is 145 mV at 300 mA under stated conditions. F1 R1max = 3.5 Ω gives a 0.210 V screen at 60 mA, minimum LDO input 4.54 V from 4.75 V. F1 hold is 200 mA at 20°C, 100 mA at 70°C and 70 mA at 85°C, with temperature rerating reference-only: margins 3.33/1.67/1.17 against 60 mA. High-temperature operation is not generously qualified.
At 5.25 V and 60 mA, the LDO output-load dissipation upper screen is 0.117 W; DBV RθJA = 187.1°C/W gives about 21.9°C rise on the datasheet test board, not this PCB. No-load IGND of 6.5 µA typical / 8.5 µA maximum at 6 V / 25°C is not a loaded-current maximum; at 300 mA the table gives 2 mA typical without a maximum. Use a provisional 2 mA input-current allowance, explicitly not guaranteed, for external power/F1 screens; 62 mA slightly reduces hold margins. Actual thermal/inrush/loaded current remains a measurement gate.
See Passive Package Qualification for every resistor stress screen. Normal low-voltage DC supports 0402 ordinary resistors, not unrestricted rail-short or ESD ratings. R1 has an initial nominal 3.3 V / 10 Ω demand of 1.089 W into discharged analog capacitance; R24 with continuous 3.3 V across its minimum resistance would demand about 110 mW, above its generic 63 mW property. Inrush/fault/pulse qualification remains open; these conditions are not declared safe. Exact RC limiter DC margins do not establish medical barriers.
C1/C4/C5/C10/C11 remain 0603 pending exact effective-C/ESR qualification; no universal smaller-package unavailability is claimed. C11 requires 4.7 µF ceramic and ESR <1 Ω at actual core bias, not merely a nameplate. U2 needs 0.47–200 µF effective output capacitance and ESR ≤100 mΩ; generic placeholders are not proof. C23 is the sourced stable 1206 exception. Y1 exact CL and oscillator startup/frequency accuracy remain gates; nominal 12 MHz and 18 pF capacitors alone do not validate USB timing.
No official nonlinear AD8232 model was successfully executed. A model-download attempt failed; these results must never be relabeled vendor-model validation. No firmware, Python or simulator scripts are deliverables; the equations, inventory, test conditions and numerical evidence above are the reproduction record.
Required electrode-simulator tests: supply ramps/load steps and measured 3V3A; reference load/noise/stability; calibrated sweeps in both jumper states at all internal nodes; offset/artifact/open-lead/reconnect recovery; complete source-specific noise/alias/ADC ENOB; switched ADC settling/mux history; real RLD cable/contact/isolated-return behavior; defined-pulse clamp/backpower/ESD coordination; procurement/pad/paste/DC-bias qualification. Qualified whole-system isolation/leakage/fault review is mandatory before human connection. Documentation/small-signal batch completion is separate from system release.
1. Scope and verified circuit baseline
2. Complete live component inventory
Resistors — 26
Capacitors — 30
Remaining components — 15
3. All IC pins and reference fanout
U3 AD8232
U4 MCP6002
U2 TPS7A2033
U1 STM32F401CEU6 — complete physical map
4. Reproducible model and provenance
5. Executed native AC results
6. Executed DC and transient demand checks
7. Tolerance and parasitic sensitivity
8. Source-specific partial noise and SNR
Quantization separate from measured ENOB
Aliasing is source-specific
9. RLD return ratio — bounded bench starting point