PCB Feasibility
Table
| Hazard | Source | Initial Mitigation in Architecture | Open Item |
|---|---|---|---|
| Electric shock | 100 V DC output and stored capacitor energy | Output discharge MOSFET/resistor, output contactor, remote/local sense mismatch trip | Confirm enclosure, touch-safe terminals, discharge timing by test |
| Arc/fire | 3 kW bus, 40 A output, contactor matrix faults | Fuses, hard interlocks, precharge, bus brake, hardware trips | Size fuses, traces/busbars, contactors, braking resistor thermals |
| Shoot-through | Four synchronous buck phases | Gate drivers, dead time, ePWM hardware trips | Double-pulse testing, gate resistor/snubber tuning |
| Incorrect series/parallel contactor state | Off-board contactor matrix | Firmware + hardwired interlock + aux contact feedback | Detailed interlock schematic still required |
| Overvoltage on output | Sense lead failure or loop fault | Remote/local sense comparison, OVP thresholds, bus brake | Final comparator thresholds and independent OVP hardware required |
| Thermal runaway | MOSFETs, inductors, shunts, capacitors, brake/discharge resistors | Temperature sensing and fan/fault logic planned | Thermal simulation/prototype measurements required |
Status
Scope
Applicable Standards to Review
Primary Hazards
Safety-Critical Components / Interfaces
Open Safety Work