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Electrical Design Notes

Status: partial capture; electrical release blocked

77 schematic components, 56 connected nets plus three empty legacy net labels. Core capture exists for USB-C source detection, charger/system power path, digital regulation, BLE controller, bridge ADC, flash, RGB interface, buttons and debug. This is logical connectivity, not a drafted wire drawing. No PCB placement/routing, firmware, mobile app, assembled prototype or manufacturing release is complete.

Charging is intentionally inhibited in hardware: R9 pulls active-low BQ24074 CE to SYS; MCU IO9 is disconnected and marked NC. This supersedes all earlier notes claiming charge-on-by-default. Do not connect the selected battery until physical connector polarity and thermistor return are verified. Do not enable charging until the pack-specific temperature window is implemented and verified.

Durable calculation records

Earlier detailed records are retained below as supporting history; the live circuit and this status override conflicting historical claims.

Captured architecture

Table

Block	Implemented direction	Qualification
USB-C	CX90M-16P; TUSB320LI UFP hardware current detection, dead-battery internal Rd; data/CC ESD and SMAJ6.0A VBUS clamp	Source-qualification static logic reviewed; transient/protection and exact connector ratings unresolved
Charger	BQ24074, all operational loads on SYS, separate BAT; default USB100 and approximately 1 A only after hardware detection of >=1.5 A source	Charger intentionally inhibited pending temperature-window design
Main rail	TPS63802, nominal 3.308 V with 511k/91k feedback; XFL4015-471MEC 0.47 uH	Critical capacitance curves and UVLO bounds not approved
Analog rail	TPS7A2033 from main 3V3 to VA_3V3A, switched by ANA_EN	Operates near dropout; guaranteed >=3 V with selected cell needs corner qualification
Sensing	ADS1220, bridge excitation also used as external reference, SPI, intended gain128/90SPS	Common-mode conditional pass; target noise/accuracy not met as a verified specification
Compute	ESP32-S3-MINI-1-N8, native USB programming, reset/boot and UART recovery	GPIO33-37 availability independently verified; reserve antenna zone before placement
Storage	W25Q128JV, 16 MiB NOR on separate SPI	Hardware connected; logging behavior not implemented
RGB	TPS2553 switched SYS supply, SN74LVC1T45 data translation, offboard connector	Exact strip unselected; must operate across actual approximately 3–4.5 V range and bounded current; ordinary 5 V-only pixels cannot be assumed compatible
Controls/debug	Two tact placeholders, RTC-capable wake button, UART/EN/boot header	Sealed switch/boot assembly not qualified; debug reference pin must not be externally powered

Storage format decision

10 Hz processed records, eight bytes/sample: int32 mass_mg, int16 flow_cg_per_s, uint8 flags, uint8 sequence. Timestamp reconstructed from start time and fixed period. 1,000 two-minute records need 9.6 MB payload. A 16 MiB flash supports 12 KiB slots plus metadata and spare capacity; longer records chain slots. Append CRC-protected records with a final commit marker, A/B calibration/configuration and wear-managed index; preserve old records when full. Raw 90 SPS samples are not all retained. Firmware and power-failure recovery are requirements, not tested behavior.

Power/runtime estimates

Historical typical budget assumed MCU40 mA, display15 mA, flash1 mA, ADC/bridge approximately6 mA, LED average15 mA and approximately90% conversion. It estimated roughly77 mA battery-equivalent and approximately6.9–11.7 h depending on load. This estimate is no longer a closed budget: the selected bare OLED's 12.5 V panel supply is uncaptured, sensing changed and pixel family remains unknown. Eight hours must be recalculated and measured. Worst-case strip/radio load and battery discharge/PCM trips must be reconciled before release; selected pack maximum continuous discharge is1 A.

Sourced off-board constraints

TAL220B drawing: selected5 kg,1.0±0.1mV/V, excitation3–10V, approximately1k input bridge. Red E+, black E-, green S+, white S-. Capacity headroom does not prove 0.1 g performance. Current ADS1220 typical-noise estimate with this cell is about0.28 g RMS/sample and0.09 g RMS at a10Hz average; supply/reference conditions, filtering and real noise require measurement.
LP543450 specific pack drawing: 1S1000mAh protected PHR-3/PCM/10kNTC variant, standard200mA/max500mA charge, +10 to+45C charging,1A maximum continuous discharge; protection cutoff2.70–2.80V. Physical pin numbering and NTC return remain unverified.
WEO012864ALAP3N00000 datasheet: SSD1309 OLED, no backlight, VDD2.8–3.3V and VCC12–13V,24-contact0.5mm FPC. Requires dedicated panel power/application parts and sequence; FPC handedness/contact face unverified. No display circuit or connector is captured. Do not connect raw3V3 whose tolerance reaches approximately3.398V directly to this panel.

Independent review and current blockers

Table

Item	Evidence/disposition	Needed to close
ADC common-mode	Original ADS1232/3V circuit failed; replaced ADS1220 topology reviewed	Verify VA_3V3A guaranteed excitation and measured system noise; do not claim0.1g accuracy
USB MCU sense injection	Original divider failed powered-off analysis; Q2 now isolates with3V3-only drain pullup	DC topology passed independent delta check; test attach/detach
UVLO	R16=182k,R17=165k,R38=100k,R8=100k; previous bounds omit U2 EN2 internal approximately285k pulldown. Claimed2.73V cutoff is also below selected PCM maximum2.80V	Recalculate/isolate network with guaranteed loading/leakage/tolerances; guarantee board cutoff above2.80V with margin. Current threshold annotations are NOT approved
Charging temperature	BQ default NTC window not pack's10–45C	Design/verify NTC window network or hardware monitor; keep CE inhibited meanwhile
Charge current	R6=4.99k,1%; KISET,max975 A-ohm gives197.4mA maximum	Independently passes200mA ceiling when eventually enabled; earlier984 coefficient note is superseded
No-pack/default USB boot	BAT capacitor may acquire voltage during detection	Hardware pack-presence qualification or measured proof; no guaranteed-off claim
Dead battery recovery	Charging now inhibited as safety measure	Recovery mode unavailable until thermal qualification and controlled charging are implemented
Battery harness	Pin1/NTC return unknown, no board reverse-polarity protection	Vendor confirmation or sample continuity/voltage check before connection; verify PCM and1A continuous/peak budget
Display	Entire OLED power/logic/FPC block absent	Verified FPC mating geometry, panel boost/sequence and logic-supply/interface design
Critical capacitors	C2/C5/C6/C7 GRM21BR61E226ME44L footprints confirmed0805; C9 GRM155R61A225ME95D	Manufacturer effective capacitance curves at bias/temp/tolerance unavailable; do not release with estimates
USB detector	OUT1 pullup toSYS respects absolute maximum; functional pullup range at4.5V not confirmed	Manufacturer confirmation or revised guaranteed interface
Inductor/protection	Operating current margin acceptable; at5.75A limit L drops20–30%; input TVS/CC ESD transient coordination incomplete	Define fault/surge waveform, qualify current-limit and downstream overshoot/CC clamp behavior
Controls/pixels	Tact placeholders and strip connector only	Exact sealed switch and strip ratings, harness, current/brownout/thermal tests
Mechanical fit	36 valid placed solids; Timer boot/lid interference2.88037mm3 remains	Targeted geometry repair and fit recheck; FPC/USB/board positions and print tolerances not released

Verification evidence

Read live automatic ERC after the safety edits:17 errors, consisting of15 undriven-pin reports and two duplicate-OUT driver/pin conflicts on the same charger. Independent inspection explains the parallel OUT pins and passive/MCU-driven paths as metadata limitations; TS and bridge input explanations remain conditional on real off-board connections. No floating pins or single-pin connected nets were reported by capture checks. Nonzero ERC is not a clean release, and ERC cannot detect the UVLO or uncaptured display issues. Only the original ADC RC/enable-divider models were simulated; no regulator SPICE models were available and no revised full power-chain simulation was run. No physical tests, completed PCB DRC or manufacturing files exist. Final safety edit: CE pullup powered steady state independently passed; R9 tolerance still needs released-BOM specification.

Next work, in priority order

Resolve battery thermal/UVLO/startup and harness qualification; keep charge inhibited until passed.
Finish OLED connector/power/logic capture; select strip and sealed controls; qualify capacitor data.
Repair Timer boot interference and coordinate real populated PCB/USB/antenna fit.
Repeat focused verification of the remaining items, then approve schematic drafting and PCB placement; present placement before routing.
Complete full bring-up/compliance documents once the missing circuit blocks and power-on safety gates are closed. No released bring-up procedure should instruct connecting the unresolved pack.

Status: partial capture; electrical release blocked
Durable calculation records
Captured architecture
Storage format decision
Power/runtime estimates
Sourced off-board constraints
Independent review and current blockers
Verification evidence
Next work, in priority order