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Schematic

Layout

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Design Notes
Rev A MCU and Inverter Architecture
  • MCU: STM32G473CBT6, 170 MHz Cortex-M4F in LQFP-48, selected for advanced motor-control timers, synchronized ADC resources, fast break/fault inputs, input capture, and SWD.
  • Gate driver: DRV8323SRTAR, 6–60 V three-phase smart gate driver with SPI, three low-side current-shunt amplifiers, charge pump, VDS protection, and hardware fault output.
  • Power MOSFETs: six BSC010N04LS6ATMA1, 40 V N-channel devices in 5 × 6 mm PG-TDSON-8. Datasheet headline limits: 1.0 mΩ max at 10 V, 1.4 mΩ max at 4.5 V, 67 nC typical total gate charge.
  • Current sensing: three 1 mΩ CSS4J-4026R-1L00F four-terminal 4 W Kelvin shunts, one per low-side leg, routed to the driver CSAs.
  • Logic supply: TPS62172DSGT fixed 3.3 V, 0.5 A synchronous buck from the 6.0–8.4 V battery rail.
Preliminary Power Budget

Table

Rail/pathContinuous estimatePeak budgetBasis
3V3 MCU, ADC dividers, NTC and debug0.20 A0.30 AConservative Rev A allocation; regulator rated 0.5 A
Gate-driver bias and gate charging~0.02 A from BAT+switching-dependent67 nC MOSFET gate charge; verify against PWM frequency and programmed drive current
Future BEC input~2.3 ATBDUser-provided common-path allowance; BEC itself not implemented in this batch
Motor path30 A target80 A short transient targetRequires PCB copper, airflow and thermal validation
Common battery path~32.3 A continuous targetmotor-dominated transientAnnotate connector, net and copper accordingly
Sensing Targets
  • 1 mΩ shunt produces 30 mV at 30 A and 80 mV at 80 A. With the DRV8323 gain set to 20 V/V, nominal CSA outputs are 0.6 V and 1.6 V, respectively, within a 3.3 V ADC range.
  • Phase and battery dividers use approximately 4:1 attenuation so 12 V at the power node remains below 3.3 V; RC filtering is included at each ADC input.
  • Power-stage temperature is measured with a 10 kΩ B3950 NTC divider to 3.3 V.
Explicit Risks for PCB Phase
  • The 30 A continuous target is not established by MOSFET current ratings. It depends on copper weight, via arrays, switching frequency, dead-time, airflow, board area, and measured junction temperatures.
  • The XT30-family battery connector and motor-wire terminals require confirmation against the exact mating system and thermal rise at the intended duty cycle.
  • 40 V MOSFET margin is intentional for 2S switching spikes, but transient suppression and power-loop inductance still require layout validation.

  • Rev A MCU and Inverter Architecture

  • Preliminary Power Budget

  • Sensing Targets

  • Explicit Risks for PCB Phase