DECT NR Plus Intercom

flux

Ho letto e consolidato la documentazione R2 e avviato lo schema Rev A. Il progetto ora contiene 53 componenti e 45 reti, inclusi nRF9151, nRF5340, power path, MAX17055 con reti Kelvin, collegamento SPI tra MCU, ES8388/I²S e catena RF 50 Ω.
Lo schema non è ancora pronto per il layout:
  • L’esecutore iniziale ha riportato 235 segnalazioni ERC.
  • Mancano ancora verifiche/completamenti per decoupling e pin riservati dei due MCU, shunt Kelvin reale, protezione batteria, consenso USB-C, watchdog/CE, NTC, matrici K1, PTT, UI, debug e test point.
  • Pinout OLED e alcuni dati meccanici restano non verificati.
  • Ho rimandato lo schema allo stesso esecutore con istruzioni precise per completare questi punti e ridurre l’ERC, ma non ho potuto recuperarne il nuovo rapporto finale.
  • Nessun placement, routing o layout PCB è stato avviato: procedere con uno schema ancora non verificato sarebbe rischioso.
Il prossimo passo è recuperare il risultato dell’ultima correzione, eseguire una review indipendente dello schema e, solo dopo ERC accettabile, configurare il PCB JLCPCB a sei strati e iniziare placement e routing.
L’esecuzione si è fermata perché gli ACUs sono terminati.
"Beltpack Schematic Rev A" completed.

flux

Non ho potuto recuperare né riconciliare il report dell’executor “Beltpack Schematic Rev A”, quindi non posso confermare che lo schema sia corretto o pronto per il layout. In questa sessione non sono state apportate ulteriori modifiche a schema o PCB.
Restano da completare:
  • verifica indipendente di componenti, collegamenti, alimentazioni ed ERC;
  • confronto dello schema con i documenti di specifica allegati;
  • correzione degli eventuali errori;
  • definizione del budget di potenza;
  • solo dopo la validazione dello schema: stackup JLCPCB a 6 strati, profilo scheda, placement, vincoli RF/antenna e routing controllato;
  • checkpoint di approvazione tra schema verificato e layout.
L’esecuzione si è fermata perché gli ACUs disponibili sono esauriti.
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Schematic

Layout

3D View

Rev A Design Notes
Power budget baseline
  • User baseline: about 0.833 W average and 1.992 W / 664 mA peak at 3.0 V for the dual-MCU system.
  • SYS is tagged for at least 0.75 A and the 3.3 V regulator path for 0.40 A design capacity, above the requested 0.26 A minimum.
  • TPS63802 support uses the datasheet 3.3 V application values: 0.47 uH, 10 uF input, 22 uF output, and 511 kΩ / 91 kΩ feedback.
  • MLCC values are nominal; layout/BOM selection must verify effective capacitance under DC bias and temperature.
Implemented architecture
  • Both nRF9151-LACA-R and nRF5340-QKAA-R are populated.
  • Companion link nets: COMP_SPI_SCK, COMP_SPI_MOSI, COMP_SPI_MISO, COMP_SPI_CS_N, COMP_IRQ, COMP_READY, COMP_HEARTBEAT, COMP_RESET_REQ.
  • ES8388 is codec master on AUD_BCLK and AUD_LRCK, with dedicated 12.288 MHz oscillator and separate 3.0 V analog/headphone rail.
  • Mandatory charger, gauge, CC controller, current-limited VBUS switch, external watchdog, 3.3 V buck-boost, 3.0 V LDO, holder, configurable jack connectors, OLED FPC connector, encoder, U.FL and switched RF test connector are present.
  • RF path is nRF9151 ANT -> pi tuning network -> MM8030 switched test connector -> U.FL, avoiding a T-stub. RF_ANT_50R is tagged 50 ohm.
Safety intent
  • BQ25895 CE has a default-disable pull-up component present; firmware targets are ICHG 0.896 A, VREG 4.176 V, IINLIM 1.20 A.
  • TUSB320 is present in GPIO/UFP architecture and TPS2553 ILIM baseline is 19.6 kΩ. Final discrete gating that accepts only 1.5 A/3 A advertisements remains incomplete.
  • MAX17055 Kelvin nets are named explicitly: CSP and exposed pad on BAT_RETURN; CSN on GND_SYS; BATT on BAT_SAFE+.
Blocking items before layout
  1. The nRF9151 library attachment is only a product brief, not the complete hardware design/reference schematic; mandatory reserved-ball handling, DEC0 network and full decoupling remain unverified.
  2. The nRF5340 library part has no datasheet URL; full internal-regulator capacitor network, decoupling, and clock load values remain incomplete.
  3. No verified library part was found for the required 10 mΩ, 1%, 0.5 W, four-terminal Kelvin shunt. RSH1 is a clearly marked 2-terminal schematic placeholder and is not layout-valid.
  4. No verified HS13L03W2C01 data/library part was found. J2 is a clearly labeled 10-pin 0.5 mm FPC interface; its panel pinout must be documented before wiring.
  5. Exact 2.5 mm K1 jack identity/pinout and final K1 contact mapping remain intentionally unresolved; the requested 0-ohm configuration matrices are not yet implemented.
  6. Battery reverse protection controller and dual MOSFET are placed, but the FS8205A library symbol topology must be verified against its datasheet before connecting it to the LTC4365. UV/OV divider values and hysteresis are not yet calculated.
  7. NTC1/NTC2 verified thermistor parts were not available in the library; TS/THRM networks are not complete.
  8. Charger advertisement gating, watchdog timing network, fuse and physical power switch, UI ladder, PTT filtering/protection, headphone mute/protection and audio jack matrices are not complete.
  9. Full MCU decoupling, debug headers/test points, unused-pin treatment and schematic organization/placement remain incomplete.
This file records the current state honestly: the project now contains the core Rev A architecture and several wired blocks, but it is not yet ready for PCB layout or production release.

  • Power budget baseline

  • Implemented architecture

  • Safety intent

  • Blocking items before layout