Phase 3 is underway with the power architecture first. I’m implementing the safe charger boot behavior, bidirectional fuel-gauge sensing, USB-C current detection, protected-cell interface, regulated rails, and bring-up test access before connecting the radio and audio blocks.
Phase 3 was started with the power and battery schematic assigned for implementation. That build finished, but I could not retrieve its report, inspect the resulting schematic, or perform the required independent ERC/design verification.
Current project state is therefore unverified. Remaining work:
Reconcile the completed power-block build against the specification and battery-validation requirements.
Fix any charger, gauge, USB-C, NTC, protection, regulator, or schematic-readability issues.
Build the nRF9151 radio/debug/RF block.
Build the ES8388 headset audio/PTT block.
Build the OLED and control interfaces.
Run full ERC, connectivity, datasheet, and bring-up reviews.
Stop for approval after the complete verified schematic, before PCB layout.
I could not retrieve or reconcile the executor’s “Power Battery Schematic” report, inspect its changes, or continue Phase 3 verification. The power/battery schematic remains unverified, and no additional radio, audio, UI, or PCB work was completed in this session.
Still required:
Review the executor’s exact component and connectivity changes.
Validate the charger, fuel gauge, USB-C detection, NTC, protection, and power rails against the specification.
Complete the rail-by-rail power budget and ERC review.
Fix any detected issues before implementing the radio, audio, and UI blocks.
Status: Completed research baseline for Rev A planning. No schematic capture or PCB layout has started.
Executive decisions
Table
Area
Selected Rev A direction
Fallback
Unresolved gate
DECT NR+ radio
Nordic nRF9151-LACA-R/R7
nRF9161-LACA; nRF9131 only for later cost/size optimization
Stack availability, four-node voice scheduling, latency, current, and coordinator-recovery benchmarks. Mesh is not proven.
Processor partition
Single-nRF9151 benchmark-first architecture
Add nRF5340-QKAA-R companion MCU
Keep single-SoC only if worst-case 1 encode + 3 decode/mix, encryption, OLED/UI, scheduling, recovery and logging retains ≥30% CPU and ≥25% RAM headroom.
HS HS13L03W2C01, C7465997, 1.3-inch 128×64 white SH1106 I2C OLED
Newvisio QG-2864KSWLG01, C91760, I2C/SPI
Exact FPC/connector, assembly method, mechanical drawing, display current versus content/brightness.
Main 3.3 V rail
TPS63802DLAR, C2845237, 3.3 V buck-boost
TPS63020-class if benchmarks require more transient margin
Validate final efficiency, EMI and transient response with selected inductor/capacitors.
Audio rail
TPS7A2030PDBVR, C963429, 3.0 V low-noise LDO
3.3 V TPS7A20 variant or ferrite-filtered 3.3 V if codec testing permits
Confirm ES8388 analog/digital rail split and dropout at the final upstream rail.
Battery management
BQ25895RTWT + MAX17055ETB+T + TUSB320LAIRWBR
Existing documented fallbacks
Safe-default boot, thermal, Type-C current detection and cell/holder gates remain mandatory.
Evidence and sourcing status
Radio alternatives
The nRF9151 application processor is a 64 MHz Arm Cortex-M33 with 1 MB flash and 256 KB RAM. The SiP supports 1.9 GHz DECT NR+. The full product specification also provides I2S/PDM and serial peripherals, a 3.0–5.5 V single supply, integrated clocks/PMIC, and an approximately 12.1 × 11.1 mm LGA package; these latter details were cross-checked against Nordic's current product specification but the Flux datasheet index did not return claim-level citations for every field.
Table
Candidate
Assessment
Sourcing/package note
Decision
nRF9151-LACA-R/R7
Most straightforward current Nordic choice; integrated PMIC/clocks, application core, security, DECT NR+ modem and 1.9 GHz support. Nordic recommends it for new designs over nRF9161.
Flux library part exists. JLCPCB records include C42236596 and C22397843; JLC assembly stock was zero/not confirmed at research time, so pre-order, consignment or external sourcing may be needed. LGA-113 requires X-ray inspection.
Selected.
nRF9161-LACA
Same 64 MHz / 1 MB / 256 KB application-resource class and DECT NR+ support; larger established SiP.
Cataloged by Nordic/JLCPCB; use only if nRF9151 sourcing or modem-firmware access blocks Rev A.
Fallback.
nRF9131
Smaller 11 × 7 mm SiP and firmware-compatible with nRF9161, but external PMIC, crystals and production calibration increase Rev A risk.
Not found as a ready Flux library choice during this pass.
Future cost/size option, not Rev A.
Last Mile LM10xx
Publicly announced NR+-only SoC with a faster RISC-V application class and 512 KB RAM, potentially attractive for single-chip audio.
No usable Flux/JLC/LCSC part or production datasheet was verified.
Unresolved future alternative.
Network honesty: Nordic marketing and the DECT NR+ standard discuss mesh, but the project's Phase 1 evidence found the currently available Nordic implementation supports a star baseline and does not prove the required low-latency multi-hop voice behavior. Wirepas is a separately licensed stack aimed primarily at massive-IoT profiles; it is not evidence that four-talker intercom mesh latency is acceptable. Rev A remains elected-coordinator FT/PT star unless development tests prove more.
Single SoC versus second MCU
The nRF9151 has the necessary interfaces for a codec and UI, and its modem processor owns the radio/baseband, so a single-SiP architecture is plausible. However, 256 KB application RAM is the limiting resource for multiple codec states, jitter buffers, packet-loss concealment, encrypted packet queues, display buffers, logging and RTOS stacks.
Selected decision: benchmark the single-nRF9151 path first; do not automatically add a second MCU and do not claim the single-SoC path is proven.
Pass gate for single SoC: with the chosen radio stack and a 5 or 10 ms audio frame, simultaneously run one encoder, three decoders, mixing/limiting, encryption/authentication, OLED/UI, packet scheduler, reconnect logic and diagnostics. Pass only if:
Worst-case audio-frame completion uses no more than 70% of the available frame time.
Sustained CPU utilization remains below 70%, including radio-control and logging bursts.
Peak allocated RAM remains below 75% after stack high-water measurements.
No radio deadlines, audio underruns or control watchdog deadlines are missed during coordinator operation and peer recovery.
Companion fallback: nRF5340-QKAA-R, JLCPCB C3015611, AQFN-94 7 × 7 mm. Nordic specifies a 128/64 MHz Cortex-M33 application core with 1 MB flash, 512 KB RAM, FPU/DSP instructions, I2S/PDM, and a 1.7–5.5 V supply. JLCPCB showed more than 10k units at the research snapshot. If adopted, nRF9151 owns DECT NR+ and timestamped packet transport; nRF5340 owns codec, jitter buffers, mixing, OLED/UI, K1 audio policy and product state. Use SPI with IRQ plus a framed, checksummed protocol; do not stream raw PCM over a slow UART.
Audio codec and front end
Selected: ES8388
ES8388 integrates two-channel ADC/DAC, microphone amplifier and headphone amplifier and supports 24-bit 8–96 kHz conversion plus I2S. At 3.3 V, the datasheet lists 59 mW typical for playback plus record. Its microphone PGA is adjustable from 0 to +24 dB. The device is offered in a 4 × 4 mm QFN-28 package.
Selection rationale:
C365736 was strongly stocked by both LCSC and JLCPCB during research and is an Extended part suitable for standard/economic assembly.
Integrated ADC, DAC, PGA and headphone output minimize external analog blocks for a speech prototype.
8 kHz to 96 kHz support covers 16 kHz and 24 kHz intercom sampling.
Required validation:
ES8388 documentation is inconsistent across available guides about the exact microphone-bias output. Although the register set exposes switchable microphone-bias power, Rev A shall provide an independently filtered electret-bias option and 0 Ω routing options until the final circuit is bench-validated.
Measure the final K1 microphone sensitivity, DC bias current, earpiece impedance and required output level. Keep series resistors/AC coupling and alternate routing footprints.
Validate 16 Ω and 32 Ω output, single-ended versus differential use, click/pop, hardware mute, sidetone, RF rectification and ESD robustness.
Fallback: TLV320AIC3204IRHBT
Use this if ES8388 bias/noise/documentation becomes a schedule risk. It provides 0 to +47.5 dB input PGA, I2S/PCM, programmable microphone bias and headphone drivers down to 16 Ω. Its drawback is weaker direct JLC/LCSC sourcing in the current Flux result and a more complex power/clock configuration.
Codec software order
Opus low-delay profile: preferred final codec if measured CPU/RAM and packet loss behavior pass.
LC3/LC3plus: fallback when licensing, implementation availability and measured efficiency are acceptable; DECT alignment alone does not make it automatically preferable.
IMA ADPCM: bring-up and guaranteed-low-CPU fallback.
PCM: lab-only transport/latency baseline.
No codec is production-selected until the 1-encode/3-decode benchmark and licensing/open-source review pass.
OLED and user interface
Selected display baseline: HS13L03W2C01, JLCPCB/LCSC C7465997, 1.3-inch 128 × 64 white PMOLED, SH1106 controller, I2C interface, 29.42 × 14.7 mm active area. JLCPCB listed it as an Extended assembly part with stock during the research snapshot.
Use I2C for Rev A to conserve pins; update only changed regions and cap refresh rate to reduce current and bus contention. UI controls remain a quadrature encoder with push, a 4/6-position channel selector, menu button and hard power control.
Mechanical gate: the catalog package field is unspecified. Obtain the exact drawing and sample before PCB freeze; verify FPC/connector pitch, tail direction, retention, display outline, glass keepout, viewing window, assembly temperature and serviceability. If that fails, use Newvisio QG-2864KSWLG01 / C91760 or a separately procured 4-wire module.
Preliminary rail-by-rail load and power budget
These planning values intentionally precede regulator selection. They are not claimed datasheet maxima. Radio averages, OLED current and codec workload require development-kit/prototype measurement.
Load assumptions
Table
Rail / load
Typical assumption
Peak assumption
Basis / validation status
SYS direct: nRF9151 radio + application
140 mA at 3.7 V normal mixed use
350 mA at 3.0 V during high-power TX/processing overlap
Planning assumption from Phase 1 envelope; must benchmark by role, MCS, TX power and duty cycle.
SYS direct: charger/gauge/Type-C overhead while on battery
Typical aligns with the 59 mW playback+record class at 3.3 V; peak includes margin.
3V0_AUD: earpiece output + electret bias
5 mA
35 mA
Accessory-dependent; must measure.
Rail totals
Table
Architecture
3V3_DIG typical / peak
3V0_AUD typical / peak
Reflected converter input at BAT=3.0 V peak, η=85%
Total battery typical at 3.7 V
Total battery peak at 3.0 V
Single nRF9151
33 / 85 mA
25 / 70 mA
(3.3×0.085 + 3.0×0.070) / (3.0×0.85) = 0.192 A
0.140 + (0.1089+0.075)/(3.7×0.90) + 0.003 ≈ 0.198 A / 0.73 W
0.350 + 0.192 + 0.010 = 0.552 A / 1.66 W
nRF9151 + nRF5340
58 / 165 mA
25 / 70 mA
(3.3×0.165 + 3.0×0.070) / (3.0×0.85) = 0.296 A
0.140 + (0.1914+0.075)/(3.7×0.90) + 0.003 ≈ 0.223 A / 0.83 W
0.350 + 0.296 + 0.010 = 0.656 A / 1.97 W
Coordinator planning: if the measured nRF9151 average rises to 250 mA at 3.7 V, expected continuous input becomes approximately 1.14 W single-SoC or 1.24 W dual-processor. With roughly 9.5–10.5 Wh usable from the locked 3500 mAh-class protected cell after cutoffs and conversion losses, normal mixed-use planning is about 11–14 h and continuous coordinator planning about 7.5–9 h. Both remain measurement-dependent.
The battery holder path should therefore pass at least the calculated 0.66 A system peak with margin, but no current capability is assigned to BK-18650-PC2 until supplier confirmation or temperature-rise/contact-drop testing establishes it.
Regulator recommendations after budget
3V3_DIG: TPS63802DLAR
TPS63802 accepts 1.3–5.5 V, provides an adjustable output and is rated for 2 A at 3.3 V when input is at least 2.3 V, with 11 µA operating quiescent current. This comfortably exceeds the calculated 165 mA 3.3 V peak and maintains regulation as the single-cell SYS rail crosses 3.3 V. JLCPCB C2845237 showed strong assembly stock.
Initial implementation direction from the datasheet is a 0.47 µH inductor and 22 µF nominal output capacitance for output voltages at or below 3.6 V. Final inductor saturation current, RMS current, MLCC DC-bias derating and transient response must be calculated from the final load and layout.
3V0_AUD: TPS7A2030PDBVR
TPS7A20 is a 300 mA low-noise LDO family with 1.6–6.0 V input, 6.5 µA typical quiescent current, approximately 7 µV RMS noise and high PSRR; the fixed 3.0 V DBV variant is JLCPCB C963429 and showed strong assembly stock. The 300 mA rating exceeds the 70 mA preliminary audio peak. Feed it from 3V3_DIG so its dissipation is only about (3.3−3.0)×0.025 = 7.5 mW typical and 21 mW at the planning peak.
nRF9151 supply
Power nRF9151 from the BQ25895 SYS path directly if the final Nordic reference design and SYS operating range remain compatible with the SiP's 3.0–5.5 V input. This avoids converting the radio's pulsed load through the 3.3 V rail. Provide local bulk/high-frequency decoupling exactly per Nordic and isolate the RF return from charger switching currents. Add a current-measurement link for development testing.
BQ25895RTWT: locked switch-mode charger/power path; CE defaults disabled until firmware applies safe settings.
TUSB320LAIRWBR: locked Type-C current detector; input-current policy follows source advertisement.
External nonvolatile flash: not selected for the elected-star application. Add only if the chosen radio stack, logging or FOTA image strategy proves it necessary. Wirepas-specific external-flash requirements do not automatically apply to the custom star baseline.
Required validation before schematic capture
Obtain/access the exact nRF9151 DECT NR+ modem/MAC release intended for Rev A and confirm band 1 operation, licensing and redistribution constraints.
Run four-node synthetic payload tests and measure throughput, latency, jitter, packet loss, coordinator loss/re-election and power; do not claim mesh.
Benchmark Opus, LC3/LC3plus and ADPCM with 1 encode + 3 decode/mix paths on nRF9151; repeat on nRF5340 if the single-SoC gate fails.
Bench ES8388 with the actual K1 headset: bias, gain, noise, output level, mute/pop, sidetone, ESD and RF immunity.
Obtain and sample the HS13L03W2C01 mechanical/FPC assembly details and measure display current for representative UI pages.
Validate TPS63802 and TPS7A2030 startup, transient response, efficiency, ripple, audio noise and RF spurs using the measured loads.
Recheck JLCPCB stock at BOM lock, especially nRF9151 and the OLED; pre-order or consign where required.
Complete all P1835J/BK-18650-PC2 incoming-inspection, current/contact and NTC gates in the battery validation report.
Scope completion
Radio/SoC alternatives: completed for Phase 2 baseline, with nRF9151 selected and mesh explicitly unresolved.
Single-SoC versus second MCU: completed as a conditional decision, single-SoC benchmark first and nRF5340 selected fallback.
Codec/audio front end: completed as a candidate selection, ES8388 selected with TLV320AIC3204 fallback and accessory/bias gates.
OLED/UI: completed as a sourcing baseline, HS13L03W2C01 selected with mechanical gate.
Rail budget and regulators: completed preliminarily, with explicit assumptions and dev-kit/prototype benchmark requirements.