I’ll reorganize the PCB so the LED display is centered and visually balanced on the circular face, with the coin-cell holder moved to the back, then check overlaps and board-edge clearance.
The board is currently a 45 × 38 mm rounded rectangle, with 12 LEDs in two rows and the battery holder on top. I propose a 45 mm circular board, a centered 3 × 4 LED grid on the front, buttons along the right edge, and the CR2032 holder on the back; other circuitry stays around the display where practical.
Confirm this arrangement and I’ll implement the placement.
Completed — MCU power and grounds: Both VDD pins, all three VSS pins, VDDA/VSSA, VDDUSB, and VBAT were inspected. They are connected to the protected VDD/GND rails. VBAT tied to VDD is the specified arrangement when there is no separate backup source.
Completed — MCU decoupling: Four 100 nF ceramic capacitors remain on VDD, covering the two VDD pins plus the separately supplied VDDUSB/VBAT domains. The datasheet requires one 100 nF ceramic capacitor per VDD pin, close to the supply pair. VDDA retains parallel 1 µF and 10 nF ceramic decoupling to VSSA, matching the datasheet recommendation.
Completed — reset: Added C_NRST = 100 nF ceramic from NRST to GND. The MCU has a permanent internal NRST pull-up and the recommended external circuit uses 0.1 µF to ground.
Completed — BOOT0: Existing R_BOOT1 = 10 kΩ pulls PH3/BOOT0 low for deterministic normal startup. No architectural change was made.
Completed — SWD: J1 is electrically usable: pin 1 VDD reference, pin 2 SWDIO/PA13, pin 3 GND, pin 4 SWCLK/PA14, pin 5 NRST, pin 6 intentionally NC. PA13, PA14, and NRST assignments match the MCU pin table.
Completed — unused MCU pins: Marked PC13, PH0, PH1, PA8–PA12, PA15, PB2–PB9, and PB15 intentionally no-connect. Firmware should configure unused GPIOs as analog/no-pull for lowest leakage; the datasheet uses all-I/O-analog mode for low-current characterization.
Completed — LSE crystal: Y1 is correctly between PC14/LSE_IN and PC15/LSE_OUT with one capacitor from each side to GND. Changed C_X1 and C5 from 10 pF to 8.2 pF ceramic. The fitted crystal is the 6 pF-load variant; 8.2 pF per side is the nearest standard value for approximately 6 pF effective load with about 1.9 pF combined pin/PCB stray capacitance. No external oscillator resistor was added; ST explicitly says not to fit one. Crystal ESR is 70 kΩ maximum and drive level is 0.5 µW maximum.
Completed — battery path: The two holder positive contacts join VBAT_RAW, then feed D_PROT1 anode; its cathode feeds VDD. Battery negative is GND. This is the correct polarity for a series reverse-installation Schottky path. C_BULK1 = 4.7 µF remains across protected VDD/GND to buffer display pulses. The STM32 VDD operating range is 1.71–3.6 V, so a CR2032 after a low-drop Schottky remains electrically plausible.
Completed — LED display: Audited all 12 LEDs (D1 and LED1–LED11). Each has its own 1 kΩ series resistor (R1–R12), with MCU GPIO → resistor → LED anode and LED cathode → GND. The LED has 1.9 V typical forward voltage at 2 mA. At a nominal protected rail near 2.7–2.9 V, each branch is roughly 0.8–1.0 mA; twelve simultaneous branches are roughly 10–12 mA. This is well below the MCU's 20 mA per-pin and 100 mA summed source limits, but it is a heavy pulse for a CR2032 and should remain brief.
Completed — buttons: SW1/SW2/SW3 are SPST normally-open switches to GND. Added 100 kΩ external pull-ups R_BTN_DISPLAY, R_BTN_MODE, and R_BTN_SET from VDD to their active-low nets. This prevents floating inputs during reset/before GPIO initialization while limiting held-button current to about 30 µA each.
Completed — ERC/design review: Post-edit electrical and passive-component review returned no open errors, warnings, or uncertain findings. Connectivity was also inspected directly rather than relying on ERC alone.
Issues found and exact corrections
NRST lacked the datasheet-recommended capacitor. Added C_NRST, 100 nF ceramic, NRST-to-GND, tagged as reset decoupling/filter.
All three button inputs depended entirely on firmware-configured internal pulls. Added three 100 kΩ external pull-ups, one per active-low button, with role details.
LSE load capacitors were 10 pF each despite a 6 pF-load crystal. Changed both to 8.2 pF and updated role metadata.
Unused MCU pins and the spare SWD header pin were not explicitly documented as unused. Added no-connect markers to all 18 unused GPIOs and J1 pin 6.
Verified, not changed: all 12 LED branches already had individual 1 kΩ resistors and correct polarity; MCU supply/ground domains, BOOT0 pull-down, SWD signal mapping, VBAT tie, holder polarity, Schottky direction, and bulk/decoupling connectivity were already logically correct.
Remaining risks / justified warnings
D_PROT1 is still a generic SMA Schottky with no real MPN or guaranteed forward-drop/leakage specification. Electrically the topology is correct, but SMA is physically large for a watch and an unspecified diode prevents a defensible battery-life/minimum-voltage calculation. Before manufacturing, select a low-leakage, low-VF small-package Schottky and re-check end-of-life CR2032 voltage margin.
Crystal capacitance remains layout-dependent. 8.2 pF is a calculated starting value for the 6 pF crystal, not a production trim guarantee. Keep Y1 and both capacitors very close to PC14/PC15, avoid copper/noisy traces beneath the oscillator, and provide a measurement/tuning option if watch accuracy is critical.
Simultaneous LED load is intentionally preserved. A 10–12 mA display pulse is plausible but aggressive for a CR2032. Firmware should illuminate only on demand, use short duty cycles, and avoid leaving all bits continuously on.
SWD header is a nonstandard 2×3 pin order. It is electrically usable, but the programming cable must match the documented mapping; it is not the ARM Cortex 10-pin standard.
New passives were added to the schematic only. Their PCB placement/routing must be incorporated near the associated buttons/NRST before fabrication.