Linux Cyberdeck Design

flux

There’s still a moderate amount left before this is a full manufacturable board. The first-pass schematic is started, but we are not ready for PCB layout/manufacturing yet.
Main things still left to figure out
  1. Display connection
    • Exact Waveshare 6.25" DSI LCD-B connector pinout
    • DSI lane count
    • Backlight power/current
    • Touch interface, if any
    • Correct FPC connector part
  2. Battery and power
    • Exact 10,000 mAh battery pack
    • Battery connector/current rating
    • Battery protection/NTC details
    • Confirm charger settings for that pack
    • Validate 5 V boost converter can handle CM5 + LTE + display + USB-A peaks
  3. Protection parts
    • USB-C ESD protection
    • USB-A USB 3.0 ESD protection
    • HDMI ESD protection
    • SIM card ESD protection
    • Possibly battery/input fuse or protection
  4. Regulator final values
    • Final inductor part numbers
    • Capacitor voltage/package choices
    • TPS61288 compensation check
    • Thermal/current margin check
    • Layout-sensitive switching-node constraints
  5. CM5 details
    • Decide whether to add RTC backup for CM5 VBAT
    • Decide whether to expose nRPIBOOT/service pads
    • Confirm GPIO assignments for LTE, audio, IMU, keyboard wake
  6. LTE/SIM7600 details
    • Confirm exact SIM7600G-H-M.2 hardware guide handling for VDD_AUX and VDD_1V8
    • Confirm LTE/GNSS antenna connector placement strategy
    • Add SIM ESD
    • Add RF/layout keepout rules
  7. Keyboard board
    • Main-board FPC is planned, but keyboard PCB itself still needs to be designed
    • Need switch/keycap sourcing
    • Need keyboard RP2040 schematic/firmware pin map finalized
  8. Mechanical basics
    • Rough board size
    • Port locations
    • Battery location
    • Screen/keyboard placement constraints
    • Mounting holes
    • Antenna placement/keepouts
  9. PCB layout setup
    • Stackup choice, likely 6-layer because of USB 3.0, HDMI, MIPI DSI, RF, and power density
    • Controlled-impedance rules
    • Differential-pair rules
    • Power trace/current rules
    • Thermal copper areas
  10. Bring-up and manufacturing prep
  • Test pads
  • Debug headers
  • Board bring-up checklist
  • BOM cleanup
  • Footprint review
  • DRC
  • Gerbers/BOM/pick-and-place
My estimate
Schematic is roughly 55–65% figured out.
Full board readiness is more like 30–40% complete, because layout, power validation, protection, display details, and mechanical constraints are still significant.
The biggest blockers are:
  1. Exact display connector/pinout
  2. Exact battery pack
  3. Power validation for the 5 V rail
  4. ESD/protection parts
  5. Mechanical board size/port placement
  6. Keyboard PCB design
Once those are decided, the remaining work becomes much more straightforward.
Power, display, protection
Find display pinout
Validate power rail
Add protection parts
Add test pads
Review battery connector

Waiting for input

Sign up to send

Files

Schematic

Layout

3D View

Schematic Capture Status — Linux Cyberdeck
Status
First-pass schematic capture for the Raspberry Pi CM5 carrier has been started and the main functional wiring is in place.
Implemented Blocks
  • Raspberry Pi CM5 Lite carrier power input pins and all CM5 grounds.
  • USB-C charging/data connector routed as USB 2.0 gadget/rpiboot data path to CM5 USB2.
  • TPS25730 USB-C PD sink controller with bypass capacitors and ADCIN straps for a first-pass 9–15 V / 3 A sink profile.
  • BQ25792 1S Li-ion charger/power-path first-pass support: inductor, bootstrap caps, REGN cap, TS NTC divider, PROG strap, VAC sense, CE, ILIM, SDRV no-ship-FET cap.
  • TPS61288 5 V boost rail for CM5, USB-A VBUS switch, audio, and peripherals; includes inductor, bootstrap cap, feedback divider, output caps, and provisional compensation.
  • TLV62569 3.3 V peripheral buck rail with inductor, feedback divider, input/output capacitors.
  • TPS63020 3.9 V LTE buck-boost rail for SIM7600 VBAT pins.
  • USB-A 3.0 host connector via CM5 USB3 port 0 and TPS2553 current-limited VBUS switch.
  • USB2514B internal USB 2.0 hub on CM5 USB3 port 1 USB2 companion pair, with downstream ports to SIM7600 LTE and keyboard FPC.
  • 6-pin keyboard FPC: 3V3, GND, USB D+/D-, wake/powerbutton, spare.
  • microSD boot/storage socket wired to CM5 SD interface.
  • HDMI0 Type-A connector wired to CM5 HDMI0 data, clock, DDC, CEC, HPD, 5 V, and grounds.
  • MAX98357A I2S mono speaker amp wired to CM5 GPIO/I2S pins and speaker connector.
  • BMI270 IMU wired to shared I2C bus and interrupt GPIOs.
  • MAX17048 fuel gauge wired to 1S battery and shared I2C bus.
  • SIM7600 LTE/GNSS M.2 module wired for power, USB, SIM, RF, power key, reset, flight mode, and status.
  • Nano SIM socket added and wired to SIM7600 USIM pins.
Final ERC Snapshot
The final electrical check has four remaining errors, all treated as documented exceptions for this schematic pass:
  1. U1 VBAT — CM5 RTC backup battery input is not populated. Do not connect to the 1S LiPo directly; CM5 VBAT max is lower than full LiPo voltage. Add a coin cell/supercap/regulated RTC backup later if desired.
  2. J12 VPP — Nano SIM VPP is unused for modern SIM operation. The library classifies it as a power input even though it is intentionally unconnected.
  3. U11 VDD_1V8 — SIM7600 library classifies this as a power input. In this carrier pass it is left unused/auxiliary; verify against the exact SIM7600G-H-M.2 hardware guide before layout.
  4. U11 VDD_AUX — SIM7600 library classifies this as a power input. In this carrier pass it is left unused/auxiliary; verify against the exact SIM7600G-H-M.2 hardware guide before layout.
Known Open Risks Before Layout
  • DSI display is not wired yet. The library did not have the exact Waveshare 6.25 in DSI LCD-B connector/pinout; the provisional FPC connector is intentionally no-connected until the exact connector and pinout are confirmed.
  • USB ESD arrays were removed because the selected TVS array pin names were not usable without verifying pin mapping. Re-add USB-C, USB-A, SIM, HDMI, and external connector ESD protection before layout.
  • Power-stage values are provisional. TPS61288 compensation, inductor saturation, thermal margin, and output capacitance need a full power design calculation before PCB layout.
  • Battery connector is provisional. JST-PH is not appropriate for final high-current 10 Ah pack unless the actual pack current is low enough; choose final battery connector after battery pack selection.
  • 3.3 V peripheral domain and CM5 GPIO_VREF need review. Current pass ties GPIO_VREF to 3V3_PERIPH for logic compatibility; review back-power behavior and sequencing before layout.
  • SIM7600 auxiliary pins need exact datasheet confirmation. VDD_AUX and VDD_1V8 handling must be verified against the exact module hardware design guide.
  • Bring-up/debug connectors are still minimal. Add test pads for 5V_SYS, 3V3_PERIPH, SYS_BAT, BAT_1S, PD_PPHV, PMIC I2C, nRPIBOOT, PMIC_ENABLE, LTE PWRKEY/RESET, and UART/debug before layout.
Next Required Work
  1. Confirm exact Waveshare DSI LCD connector/pinout and wire DSI/backlight/touch.
  2. Run a detailed power budget and regulator sizing pass, especially TPS61288 5 V boost at low battery.
  3. Re-add ESD/protection parts with verified pin mapping.
  4. Add test pads and bring-up/debug headers.
  5. Configure high-speed differential-pair/net rules before PCB layout.

  • Status

  • Implemented Blocks

  • Final ERC Snapshot

  • Known Open Risks Before Layout

  • Next Required Work