Linux Cyberdeck Design

flux

There’s still a moderate amount left before this is a full manufacturable board. The first-pass schematic is started, but we are not ready for PCB layout/manufacturing yet.
Main things still left to figure out
  1. Display connection
    • Exact Waveshare 6.25" DSI LCD-B connector pinout
    • DSI lane count
    • Backlight power/current
    • Touch interface, if any
    • Correct FPC connector part
  2. Battery and power
    • Exact 10,000 mAh battery pack
    • Battery connector/current rating
    • Battery protection/NTC details
    • Confirm charger settings for that pack
    • Validate 5 V boost converter can handle CM5 + LTE + display + USB-A peaks
  3. Protection parts
    • USB-C ESD protection
    • USB-A USB 3.0 ESD protection
    • HDMI ESD protection
    • SIM card ESD protection
    • Possibly battery/input fuse or protection
  4. Regulator final values
    • Final inductor part numbers
    • Capacitor voltage/package choices
    • TPS61288 compensation check
    • Thermal/current margin check
    • Layout-sensitive switching-node constraints
  5. CM5 details
    • Decide whether to add RTC backup for CM5 VBAT
    • Decide whether to expose nRPIBOOT/service pads
    • Confirm GPIO assignments for LTE, audio, IMU, keyboard wake
  6. LTE/SIM7600 details
    • Confirm exact SIM7600G-H-M.2 hardware guide handling for VDD_AUX and VDD_1V8
    • Confirm LTE/GNSS antenna connector placement strategy
    • Add SIM ESD
    • Add RF/layout keepout rules
  7. Keyboard board
    • Main-board FPC is planned, but keyboard PCB itself still needs to be designed
    • Need switch/keycap sourcing
    • Need keyboard RP2040 schematic/firmware pin map finalized
  8. Mechanical basics
    • Rough board size
    • Port locations
    • Battery location
    • Screen/keyboard placement constraints
    • Mounting holes
    • Antenna placement/keepouts
  9. PCB layout setup
    • Stackup choice, likely 6-layer because of USB 3.0, HDMI, MIPI DSI, RF, and power density
    • Controlled-impedance rules
    • Differential-pair rules
    • Power trace/current rules
    • Thermal copper areas
  10. Bring-up and manufacturing prep
  • Test pads
  • Debug headers
  • Board bring-up checklist
  • BOM cleanup
  • Footprint review
  • DRC
  • Gerbers/BOM/pick-and-place
My estimate
Schematic is roughly 55–65% figured out.
Full board readiness is more like 30–40% complete, because layout, power validation, protection, display details, and mechanical constraints are still significant.
The biggest blockers are:
  1. Exact display connector/pinout
  2. Exact battery pack
  3. Power validation for the 5 V rail
  4. ESD/protection parts
  5. Mechanical board size/port placement
  6. Keyboard PCB design
Once those are decided, the remaining work becomes much more straightforward.
Power, display, protection
Find display pinout
Validate power rail
Add protection parts
Add test pads
Review battery connector

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Schematic

Layout

3D View

Raspberry Pi CM5 Carrier Direction — Linux Cyberdeck
Status
Selected compute-platform direction. The cyberdeck will use a Raspberry Pi Compute Module 5 (CM5) mounted to the custom carrier board instead of an RK3588-class SOM or raw RK3588S2 design.
Selected CM5 Module
Selected DigiKey part:
  • DigiKey URL: https://www.digikey.com/en/products/detail/raspberry-pi/SC1598/25805587
  • Manufacturer: Raspberry Pi
  • MPN: SC1598
  • Raspberry Pi SKU string found: CM5108000
  • Description: Raspberry Pi Compute Module 5, 8 GB RAM, Lite / 0 GB eMMC, wireless
  • Storage direction: carrier-board microSD slot via CM5 Lite SDIO storage interface.
  • Wireless direction: Wi-Fi/Bluetooth-capable CM5; antenna clearance or external U.FL strategy must be handled mechanically.
Why CM5 Fits This Project
  • CM5 already includes the processor, LPDDR4x, PMIC/power sequencing, boot-critical hardware, and Raspberry Pi software ecosystem.
  • It aligns well with the selected Waveshare 6.25inch DSI LCD (B), which is documented for Raspberry Pi DSI overlays.
  • It exposes enough interfaces for the cyberdeck: USB 3.0, USB 2.0, HDMI, MIPI DSI/CSI, PCIe, Ethernet PHY, GPIO/I2C/SPI/UART/I2S, optional Wi-Fi/Bluetooth.
  • It avoids raw DDR/BGA compute-board risk while still allowing a custom carrier for battery, LTE/GNSS, LoRa, keyboard, display, audio, and enclosure-specific connectors.
CM5 Carrier Interfaces Relevant to This Design

Table

FunctionCM5 CapabilityCyberdeck Use
Main power5 V input, pins 77/79/81/83/85, 4.75–5.25 VHigh-current 5 V rail from battery/USB-C power path
USB 3.0Two SuperSpeed host portsOne external USB-A 3.0; second not used for USB-C gadget mode
USB 2.0 OTGOne high-speed OTG/device pathUSB-C USB 2.0 gadget/debug/rpiboot
HDMITwo HDMI 2.0 outputsOne external HDMI; second normally unused
MIPITwo 4-lane MIPI ports, DSI or CSIInternal Waveshare DSI display
SDIOExposed on CM5 LitemicroSD boot/storage slot
PCIeOne Gen 2 x1 hostNot used for NVMe baseline; optional future expansion only
EthernetIntegrated Gigabit Ethernet PHYOptional RJ45/MagJack if desired
GPIO bank1.8 V or 3.3 V via GPIO_VREFControls, I2C, UART, SPI, keyboard sideband, power signals
I2S/PWMAvailable on GPIO functionsSpeaker amplifier path candidate
RTCVBAT 2.5–3.5 VOptional coin cell/supercap
Power controlPMIC_Enable, VBUS_EN, LED_nPWR, nRPIBOOTPower button, USB VBUS switching, boot/debug
Key Datasheet Requirements Captured
Power
  • CM5 main input is a single 5 V rail.
  • 5 V input range: 4.75–5.25 V.
  • Design should support up to 2.5 A peak CM5 module consumption.
  • CM5_3.3V output is limited: 600 mA total, not a general system supply.
  • GPIO_VREF must be tied to CM5_3.3V for 3.3 V GPIO or CM5_1.8V for 1.8 V GPIO; it must not float.
  • VBAT supports RTC battery input, 2.5–3.5 V.
  • PMIC_Enable can be driven low to power off CM5.
USB
  • One USB 2.0 high-speed port.
  • Two USB 3.0 ports.
  • VBUS_EN is active high and should control downstream USB 3.0 port power.
  • USB-C direction: charging plus data; recommended first revision is sink/UFP for USB data/debug, while USB-A is the main host port.
Display
  • CM5 supports two HDMI 2.0 outputs and two 4-lane MIPI interfaces.
  • Up to three simultaneous displays are supported across HDMI/DSI/DPI.
  • HDMI requires 100 ohm differential routing, intra-pair length matching to 0.15 mm, and external ESD protection if required.
  • MIPI DSI/CSI requires 100 ohm differential routing and intra-pair length matching to 0.15 mm.
PCIe
  • One PCIe Gen 2 x1 host interface at 5 Gb/s.
  • PCIe RX requires external AC-coupling capacitors.
  • PCIe TX AC-coupling capacitors are included on CM5.
  • Baseline decision: do not use PCIe for NVMe; use microSD storage instead.
Mechanical
  • Module size: 55 mm x 40 mm.
  • Uses two 100-pin high-density connectors.
  • Mounting: four M2.5 holes inset 3.5 mm from module edge.
  • Carrier connector options include Amphenol 10164227-1001A1RLF for 1.5 mm stack height or 10164227-1004A1RLF for 4.0 mm stack height.
Diagram



  
    
  
  
    
  
















































USB-C PD + USB2 Gadget
TPS25730D PD Sink / USB2 ESD
1S2P node_8500mAh Pack
BQ25792 Charger / Power Path
Battery/System Rail
5V High-Current Boost
3.8V LTE High-Pulse Regulator
3.3V Logic Buck
Raspberry Pi CM5 SC1598
Waveshare 6.25in DSI LCD-B
USB-A 3.0 VBUS Switch
Class-D Speaker Amp
SIM7600G-H-M.2
Internal USB2 Hub / Logic
Keyboard MCU
RP2040-LoRa Board
External HDMI
microSD Slot
SIM/eSIM
LTE/GNSS Antennas
LoRa Antenna
Baseline for schematic capture:
  • USB-C provides charging plus USB 2.0 device/gadget/rpiboot data as a sink/UFP port.
  • CM5 USB 3.0 port 0 → external USB-A 3.0 with power switch/current limit and ESD.
  • CM5 USB 2.0 or an internal hub path → SIM7600 modem, custom keyboard MCU if USB HID, RP2040-LoRa board if USB, service/debug as needed.
  • Avoid full dual-role/source USB-C in the first revision unless explicitly required.
Storage Direction
  • Use microSD instead of NVMe.
  • Because the selected CM5 is Lite / 0 GB eMMC, microSD is the primary boot/storage path.
  • Add ESD protection near the socket and support card-detect if the chosen socket/pin allocation supports it.
  • PCIe can be left unused or exposed as optional future expansion pads.
Use 6 layers minimum because the carrier includes USB 3.0, USB-C data, HDMI, MIPI DSI, LTE USB, RF, and multiple power rails.
Suggested layer intent:
  1. Top signal/components.
  2. Solid GND reference plane.
  3. Power plane.
  4. Inner high-speed/signal.
  5. Solid GND reference plane.
  6. Bottom signal/components.
Open Decisions Before Schematic Capture
  1. Keyboard final layout drawing: 60-key legend, Fn map, tact/keycap part selection.
  2. Enclosure CAD kickoff: hinge selection, SMA bulkhead positions, antenna keepouts, service hatch.
  3. RJ45 Ethernet is omitted.
  4. PCIe is unpopulated test pads only.
  5. Keyboard backlight is no-stuff rev 1 with reserved footprints.
  6. Speaker output: mono/stereo, 4/8 ohm, target wattage.
  7. LTE/GNSS and LoRa antenna strategy.
  8. Mechanical enclosure dimensions and CM5 antenna clearance.

  • Status

  • Selected CM5 Module

  • Why CM5 Fits This Project

  • CM5 Carrier Interfaces Relevant to This Design

  • Key Datasheet Requirements Captured

  • Power

  • USB

  • Display

  • PCIe

  • Mechanical

  • Recommended Updated Block Architecture

  • Recommended USB Topology

  • Storage Direction

  • Recommended Stackup Direction

  • Open Decisions Before Schematic Capture