Linux Cyberdeck Design

flux

There’s still a moderate amount left before this is a full manufacturable board. The first-pass schematic is started, but we are not ready for PCB layout/manufacturing yet.
Main things still left to figure out
  1. Display connection
    • Exact Waveshare 6.25" DSI LCD-B connector pinout
    • DSI lane count
    • Backlight power/current
    • Touch interface, if any
    • Correct FPC connector part
  2. Battery and power
    • Exact 10,000 mAh battery pack
    • Battery connector/current rating
    • Battery protection/NTC details
    • Confirm charger settings for that pack
    • Validate 5 V boost converter can handle CM5 + LTE + display + USB-A peaks
  3. Protection parts
    • USB-C ESD protection
    • USB-A USB 3.0 ESD protection
    • HDMI ESD protection
    • SIM card ESD protection
    • Possibly battery/input fuse or protection
  4. Regulator final values
    • Final inductor part numbers
    • Capacitor voltage/package choices
    • TPS61288 compensation check
    • Thermal/current margin check
    • Layout-sensitive switching-node constraints
  5. CM5 details
    • Decide whether to add RTC backup for CM5 VBAT
    • Decide whether to expose nRPIBOOT/service pads
    • Confirm GPIO assignments for LTE, audio, IMU, keyboard wake
  6. LTE/SIM7600 details
    • Confirm exact SIM7600G-H-M.2 hardware guide handling for VDD_AUX and VDD_1V8
    • Confirm LTE/GNSS antenna connector placement strategy
    • Add SIM ESD
    • Add RF/layout keepout rules
  7. Keyboard board
    • Main-board FPC is planned, but keyboard PCB itself still needs to be designed
    • Need switch/keycap sourcing
    • Need keyboard RP2040 schematic/firmware pin map finalized
  8. Mechanical basics
    • Rough board size
    • Port locations
    • Battery location
    • Screen/keyboard placement constraints
    • Mounting holes
    • Antenna placement/keepouts
  9. PCB layout setup
    • Stackup choice, likely 6-layer because of USB 3.0, HDMI, MIPI DSI, RF, and power density
    • Controlled-impedance rules
    • Differential-pair rules
    • Power trace/current rules
    • Thermal copper areas
  10. Bring-up and manufacturing prep
  • Test pads
  • Debug headers
  • Board bring-up checklist
  • BOM cleanup
  • Footprint review
  • DRC
  • Gerbers/BOM/pick-and-place
My estimate
Schematic is roughly 55–65% figured out.
Full board readiness is more like 30–40% complete, because layout, power validation, protection, display details, and mechanical constraints are still significant.
The biggest blockers are:
  1. Exact display connector/pinout
  2. Exact battery pack
  3. Power validation for the 5 V rail
  4. ESD/protection parts
  5. Mechanical board size/port placement
  6. Keyboard PCB design
Once those are decided, the remaining work becomes much more straightforward.
Power, display, protection
Find display pinout
Validate power rail
Add protection parts
Add test pads
Review battery connector
J4
U11
Y1
Resistance
60 ohms
U5
J2
U4
U3
J12
J3
U1
J6
U10
U1 SD_DAT0 - J3 DAT0
U1 HDMI0_TX2_P - J4 1
U1 USB3_0_TX_P - J2 STDA_SSRX+
U4 FB_2 - R13 P2
U2 DRAIN_1 - U2 DRAIN_2
L4 P2 - U4 SW_1
U11 STATUS - U1 GPIO12
U5 VOUT - R15 P1
U6 FB - R11 P2
U2 DRAIN_1 - U2 DRAIN_2
U3 BAT_2 - U3 BATP
U3 SYS - U4 VIN_1
U11 USIM_CLK - J12 CLK
U2 ADCIN1 - R1 P2
U3 SCL - U2 I2CT_SCL
U2 ADCIN1 - R1 P2
U3 SW2 - L3 P2
U2 DRAIN_1 - U2 DRAIN_2
L6 P2 - C9 P1
U2 LDO_3V3 - C2 P1
U1 HDMI0_CEC - J4 13
U2 LDO_1V5 - C3 P1
R19 P2 - C23 P1
J1 CC1 - U2 CC1
L6 P2 - C9 P1
U1 SD_CLK - J3 CLK
U2 LDO_1V5 - C3 P1
U7 USBDM_DN2/PRT_DIS_M2 - J5 3
L6 P2 - C9 P1
U7 USBDP_DN2/PRT_DIS_P2 - J5 4
U3 SCL - U2 I2CT_SCL
U4 COMP - R19 P1
U1 USB3_0_RX_P - J2 STDA_SSTX+
U3 SYS - U4 VIN_1
J1 CC2 - U2 CC2
U1 SD_DAT3 - J3 CD/DAT3
U5 VOUT - R15 P1
J1 CC1 - U2 CC1
U2 DRAIN_1 - U2 DRAIN_2
U7 PLLFILT - C20 P1
U1 HDMI0_TX0_P - J4 7
U3 SW2 - L3 P2
U7 XTALIN/CLKIN - Y1 XTAL_1
U1 SD_CMD - J3 CMD
U1 HDMI0_HOTPLUG - J4 19
U2 PPHV_3 - U2 PPHV_4
U1 USB3_0_TX_P - J2 STDA_SSRX+
U1 GPIO18 - U10 BCLK
R19 P2 - C23 P1
U11 USIM_CLK - J12 CLK
U7 CRFILT - C19 P1
U1 GPIO19 - U10 LRCLK
R13 P1 - C13 P1
L6 P2 - C9 P1
J5 5 - U1 POWERBUTTON
U3 REGN - C25 P1
J1 DP1 - J1 DP2
U1 HDMI0_TX1_N - J4 6
R13 P1 - C13 P1
L6 P2 - C9 P1
J1 DP1 - J1 DP2
U2 LDO_3V3 - C2 P1
U11 USIM_DATA - J12 I/O
U2 ADCIN3 - R3 P2
U1 HDMI0_CLK_N - J4 12
U1 USB3_0_RX_N - J2 STDA_SSTX-
U12 INT2 - U1 GPIO25
U3 REGN - C25 P1
U2 PPHV_3 - U2 PPHV_4
U4 COMP - R19 P1
U1 +5V(INPUT)__5 - U9 IN
U3 SDA - U2 I2CT_SDA
U3 SW1 - L3 P1
U1 HDMI0_TX0_P - J4 7
U7 XTALOUT - Y1 XTAL_2
U3 PROG - R18 P1
U10 ~SD_MODE - U1 GPIO23
U10 ~SD_MODE - U1 GPIO23
U1 SD_CLK - J3 CLK
U5 L1 - U5 L1
U5 FB - R15 P2
L6 P2 - C9 P1
L6 P2 - C9 P1
U5 VOUT - R15 P1
U5 VIN - U5 VINA
U1 HDMI0_TX1_N - J4 6
U2 PPHV_3 - U2 PPHV_4
U6 FB - R11 P2
J7 1 - U3 BAT_1
U7 XTALOUT - Y1 XTAL_2
U3 SDA - U2 I2CT_SDA
U1 HDMI0_TX0_N - J4 9
U11 USIM_DATA - J12 I/O
U1 +5V(INPUT)__5 - U9 IN
HDMI0_UTILITY_NC
U11 USIM_RST - J12 RST
U3 SDA - U2 I2CT_SDA
U9 EN - U1 VBUS_EN
U3 BAT_2 - U3 BATP
U2 ADCIN4 - R5 P2
U1 HDMI0_SDA - J4 16
U1 HDMI0_CLK_N - J4 12
U5 L1 - U5 L1
U2 LDO_1V5 - C3 P1
U1 SD_DAT2 - J3 DAT2
U3 SYS - U4 VIN_1
U1 USB3_0_DP - J2 D+
J5 5 - U1 POWERBUTTON
U11 MAIN_ANT - J9 SIG
U1 SD_DAT2 - J3 DAT2
U1 SD_DAT1 - J3 DAT1
U3 SCL - U2 I2CT_SCL
U2 ADCIN4 - R5 P2
KBD_SPARE
U2 ADCIN1 - R1 P2
U2 VBUS_IN_3 - U2 VBUS_IN_4
U2 DRAIN_1 - U2 DRAIN_2
U5 L2 - U5 L2
U5 VIN - U5 VINA
U11 ~RESET - U1 GPIO6
J1 VBUS_B__1 - U2 VBUS_IN_1
U11 USIM_VDD - J12 VCC
U7 USBDP_DN2/PRT_DIS_P2 - J5 4
L6 P2 - C9 P1
R13 P1 - C13 P1
R13 P1 - C13 P1
U11 GNSS_ANT - J11 SIG
U3 BTST2 - C18 P1
U3 SW1 - L3 P1
U9 ILIM - R9 P1
U7 USBDP_DN1/PRT_DIS_P1 - U11 USB_DP
U4 SW_2 - C11 P2
U1 HDMI0_SCL - J4 15
U3 TS_2 - R20 P2
U3 PROG - R18 P1
J1 DP1 - J1 DP2
L4 P2 - U4 SW_1
U3 TS_2 - R20 P2
R13 P1 - C13 P1
J1 CC1 - U2 CC1
U12 INT2 - U1 GPIO25
U6 SW - L6 P1
L6 P2 - C9 P1
U11 GNSS_ANT - J11 SIG
U11 AUX_ANT - J10 SIG
R13 P1 - C13 P1
C11 P1 - U4 BST
J1 CC2 - U2 CC2
U5 VIN - U5 VINA
U3 SYS - U4 VIN_1
J1 DN1 - J1 DN2
U10 OUTN - J8 2
U2 LDO_3V3 - C2 P1
R7 P1 - R8 P1
U2 LDO_3V3 - C2 P1
U1 USB3_1_DM - U7 USBDM_UP
U7 RBIAS - R17 P1
L6 P2 - C9 P1
U4 FB_2 - R13 P2
C11 P1 - U4 BST
U1 GPIO21 - U10 DIN
U11 ~PWRKEY - U1 GPIO5
U5 L2 - U5 L2
U1 GPIO19 - U10 LRCLK
U1 USB3_1_DP - U7 USBDP_UP
U4 VIN_2 - U5 VIN
U3 SYS - U4 VIN_1
U1 HDMI0_HOTPLUG - J4 19
U3 BTST1 - C17 P1
U1 USB3_0_DP - J2 D+
L6 P2 - C9 P1
U4 VIN_2 - U5 VIN
U9 ILIM - R9 P1
U1 GPIO18 - U10 BCLK
U5 L2 - U5 L2
U10 OUTP - J8 1
U4 VCC - C12 P1
U1 SD_DAT1 - J3 DAT1
U7 XTALIN/CLKIN - Y1 XTAL_1
U11 AUX_ANT - J10 SIG
U11 USIM_RST - J12 RST
U11 MAIN_ANT - J9 SIG
U11 FLIGHTMODE - U1 GPIO13
U2 VBUS_IN_3 - U2 VBUS_IN_4
U1 USB3_0_TX_N - J2 STDA_SSRX-
J1 DN1 - J1 DN2
U1 HDMI0_CLK_P - J4 10
U1 USB3_0_DM - J2 D-
U2 LDO_1V5 - C3 P1
U11 ~RESET - U1 GPIO6
U1 USB3_0_TX_N - J2 STDA_SSRX-
R13 P1 - C13 P1
J1 DN1 - J1 DN2
U7 RBIAS - R17 P1
J1 VBUS_B__1 - U2 VBUS_IN_1
U2 VBUS_IN_3 - U2 VBUS_IN_4
U3 SCL - U2 I2CT_SCL
U1 HDMI0_SCL - J4 15
U6 SW - L6 P1
U1 +5V(INPUT)__5 - U9 IN
U2 LDO_3V3 - C2 P1
U7 XTALOUT - Y1 XTAL_2
U10 OUTN - J8 2
U5 L1 - U5 L1
U3 SW2 - L3 P2
U5 VOUT - R15 P1
L6 P2 - C9 P1
U9 OUT - J2 VBUS
U9 ~{FAULT} - R10 P1
U2 LDO_3V3 - C2 P1
U7 USBDM_DN2/PRT_DIS_M2 - J5 3
U11 FLIGHTMODE - U1 GPIO13
U3 BAT_2 - U3 BATP
U3 SDRV_2 - C26 P1
U4 COMP - R19 P1
U3 SDRV_2 - C26 P1
U12 INT1 - U1 GPIO24
U5 VIN - U5 VINA
U9 EN - U1 VBUS_EN
U7 USBDM_DN1/PRT_DIS_M1 - U11 USB_DN
U7 USBDP_DN1/PRT_DIS_P1 - U11 USB_DP
U1 USB3_0_RX_P - J2 STDA_SSTX+
U2 PPHV_3 - U2 PPHV_4
U7 USBDM_DN1/PRT_DIS_M1 - U11 USB_DN
U1 HDMI0_TX1_P - J4 4
R7 P1 - R8 P1
U6 FB - R11 P2
U1 GPIO21 - U10 DIN
R7 P1 - R8 P1
U3 SCL - U2 I2CT_SCL
U5 FB - R15 P2
U2 PPHV_3 - U2 PPHV_4
U2 ADCIN3 - R3 P2
U1 USB3_0_DM - J2 D-
U7 CRFILT - C19 P1
U2 VBUS_2 - U2 VBUS_3
U7 XTALIN/CLKIN - Y1 XTAL_1
U2 VBUS_2 - U2 VBUS_3
U1 SD_CMD - J3 CMD
U1 SD_DAT3 - J3 CD/DAT3
U1 HDMI0_TX2_N - J4 3
U1 SD_DAT0 - J3 DAT0
R13 P1 - C13 P1
U11 STATUS - U1 GPIO12
U1 HDMI0_CEC - J4 13
U1 HDMI0_TX2_N - J4 3
U3 BTST1 - C17 P1
U4 SW_2 - C11 P2
U1 USB3_1_DP - U7 USBDP_UP
U3 BTST2 - C18 P1
U2 VBUS_2 - U2 VBUS_3
U1 USB3_0_RX_N - J2 STDA_SSTX-
U4 FB_2 - R13 P2
U10 OUTP - J8 1
U2 ADCIN4 - R5 P2
U11 USIM_VDD - J12 VCC
U1 HDMI0_SDA - J4 16
U1 HDMI0_TX1_P - J4 4
U3 SDA - U2 I2CT_SDA
U9 ~{FAULT} - R10 P1
U5 FB - R15 P2
U3 REGN - C25 P1
U1 USB3_1_DM - U7 USBDM_UP
U5 VIN - U5 VINA
U1 HDMI0_TX0_N - J4 9
L6 P2 - C9 P1
U12 INT1 - U1 GPIO24
U3 SDA - U2 I2CT_SDA
R13 P1 - C13 P1
U7 PLLFILT - C20 P1
U11 ~PWRKEY - U1 GPIO5
U4 VCC - C12 P1
U3 SW1 - L3 P1
U1 HDMI0_CLK_P - J4 10
J7 1 - U3 BAT_1
U9 OUT - J2 VBUS
U3 TS_2 - R20 P2
U3 REGN - C25 P1
L6 P2 - C9 P1
U1 HDMI0_TX2_P - J4 1
U2 ADCIN3 - R3 P2
J1 CC2 - U2 CC2
U5 PGND - U6 GND
J3 VSS - J3 9
C23 P2 - C24 P2
U7 VSS - R17 P2
GND
U11 GND - U11 GND
U7 VSS - R17 P2
R14 P2 - C13 P2
U11 GND - U11 GND
U11 GND - U11 GND
U5 PGND - U6 GND
C1 P2 - C2 P2
J5 2 - J5 MP1
U2 GND_10 - C5 P2
GND
GND
U2 GND_5 - U2 GND_6
U11 GND - U11 GND
U7 VSS - R17 P2
J1 GND_B__1 - J1 SHIELD
J1 GND_A__1 - J1 GND_B
J4 11 - J4 17
U2 GND_10 - C5 P2
U4 AGND - U5 GND
U2 GND_5 - U2 GND_6
U8 EP - RT1 2
R14 P2 - C13 P2
J10 GND - J11 GND
J4 11 - J4 17
C1 P2 - C2 P2
U10 GAIN_SLOT - U12 GND
C1 P2 - C2 P2
U11 GND - U11 GND
C23 P2 - C24 P2
GND
U5 PGND - U6 GND
R14 P2 - C13 P2
U11 GND - U11 GND
R12 P2 - C9 P2
J3 VSS - J3 9
U11 GND - U11 GND
U7 VSS - R17 P2
C25 P2 - U3 ~CE
U11 GND - U11 GND
J1 SHIELD__1 - U2 GND_1
U11 GND - U11 GND
U2 GND_10 - C5 P2
U2 GND_10 - C5 P2
U11 GND - U11 GND
U11 GND - U11 GND
R14 P2 - C13 P2
J7 2 - U3 GND
U11 GND - U11 GND
GND
U11 GND - U11 GND
U5 PGND - U6 GND
R14 P2 - C13 P2
U11 GND - U11 GND
U11 GND - U11 GND
GND
R14 P2 - C13 P2
U9 GND - J2 GND
R12 P2 - C9 P2
J9 GND - J10 GND
U1 GND__50 - J4 2
U2 GND_10 - C5 P2
U11 GND - U11 GND
R12 P2 - C9 P2
U4 AGND - U5 GND
U8 EP - RT1 2
U7 VSS - R17 P2
J3 VSS - J3 9
U7 VSS - R17 P2
U11 GND - U11 GND
C1 P2 - C2 P2
J3 VSS - J3 9
C25 P2 - U3 ~CE
J1 GND_B__1 - J1 SHIELD
J7 2 - U3 GND
U9 GND - J2 GND
U11 GND - U11 GND
J5 2 - J5 MP1
J1 SHIELD__1 - U2 GND_1
J7 2 - U3 GND
U11 GND - U11 GND
J2 SHIELD - R9 P2
GND
R6 P2 - U2 RESERVED_1
U2 GND_5 - U2 GND_6
U2 RESERVED_2 - U2 RESERVED_3
C25 P2 - U3 ~CE
U8 EP - RT1 2
GND
U11 GND - U11 GND
GND
U11 GND - U11 GND
U11 GND - U11 GND
U7 VSS - R17 P2
J3 VSS - J3 9
C23 P2 - C24 P2
U11 GND - U11 GND
U7 VSS - R17 P2
U5 PGND - U6 GND
GND
J10 GND - J11 GND
C1 P2 - C2 P2
R14 P2 - C13 P2
R6 P2 - U2 RESERVED_1
J9 GND - J10 GND
U2 RESERVED_2 - U2 RESERVED_3
J2 SHIELD - R9 P2
J3 VSS - J3 9
J1 GND_A__1 - J1 GND_B
U1 GND__50 - J4 2
U5 PGND - U6 GND
U7 VSS - R17 P2
GND
U11 GND - U11 GND
C1 P2 - C2 P2
J3 VSS - J3 9
U5 PGND - U6 GND
U5 PGND - U6 GND
U10 GAIN_SLOT - U12 GND
U11 GND - U11 GND
C4
Capacitance
2.2uF
R2
Resistance
10kΩ
C14
Capacitance
22uF
C9
Capacitance
10uF
R3
Resistance
162kΩ
R13
Resistance
732kΩ
R17
Resistance
12kΩ
C6
Capacitance
100uF
C1
Capacitance
10uF
R1
Resistance
200kΩ
R15
Resistance
1.21MΩ
R16
Resistance
180kΩ
C23
Capacitance
1nF
C5
Capacitance
4.7uF
C11
Capacitance
100nF
R18
Resistance
6.04kΩ
C3
Capacitance
10uF
C16
Capacitance
22uF
C8
Capacitance
330pF
C15
Capacitance
22uF
R8
Resistance
3.3kΩ
C20
Capacitance
100nF
R4
Resistance
38.3kΩ
C24
Capacitance
30pF
R20
Resistance
10kΩ
C17
Capacitance
47nF
R19
Resistance
36.5kΩ
R14
Resistance
100kΩ
C7
Capacitance
330pF
C10
Capacitance
4.7uF
C18
Capacitance
47nF
C12
Capacitance
2.2uF
C26
Capacitance
1nF
C13
Capacitance
22uF
R10
Resistance
100kΩ
R11
Resistance
453kΩ
C25
Capacitance
4.7uF
C21
Capacitance
18pF
C19
Capacitance
100nF
R12
Resistance
100kΩ
R5
Resistance
200kΩ
C2
Capacitance
10uF
R9
Resistance
28.7kΩ
C22
Capacitance
18pF
R6
Resistance
10kΩ
R7
Resistance
3.3kΩ
U8
L3
Inductance
1uH
J5
L4
Inductance
2.2uH
U12
U9
J10
J9
J1
J8
J7
J11
U6
RT1
Resistance
10kΩ
L6
Inductance
2.2uH
U7
L5
Inductance
1.5uH
U2

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Architecture Risk Review — Linux Cyberdeck
Summary Recommendation
Use Raspberry Pi Compute Module 5 for the cyberdeck carrier. Do not start with a raw RK3588S2/RK3588 BGA plus discrete LPDDR4x layout unless the project scope is explicitly a high-risk compute-module development program.
Why Raw RK3588S2 + LPDDR4x Is Not Recommended
A raw RK3588S2 design is dominated by high-speed compute-board risks rather than cyberdeck feature design:
  • Fine-pitch BGA escape routing.
  • LPDDR4x length matching and impedance control.
  • DDR power integrity and timing validation.
  • PMIC selection and strict power sequencing.
  • Boot flash/eMMC integration.
  • Linux BSP / bootloader bring-up.
  • Thermal design for a high-performance SoC.
  • HDI/microvia manufacturing cost and rework difficulty.
  • Likely multiple board spins.
For a portable cyberdeck, the product value is in integration: power, screen/keyboard, LTE/GNSS, LoRa, audio, enclosure, antennas, and Linux configuration. A SOM/SBC lets the design focus there.
Practical Architecture Options

Table

OptionDescriptionProsConsRecommendation
Raspberry Pi CM5 + custom carrierUse CM5 module with custom carrier for connectors/power/radios/display/keyboardStrong Linux/display ecosystem, avoids DDR/PMIC design, good fit for Waveshare DSI displayStill requires high-speed carrier design and careful power/battery architectureSelected direction
RK3588/RK3588S/RK3588S2 SOM + custom carrierUse validated compute module with custom carrierHigher performance/NPU potentialMore vendor BSP/display risk for this screenSuperseded by CM5 choice
Raw RK3588S2 + LPDDR4x boardFull custom compute boardMaximum integrationHighest risk/cost, HDI/DDR/PMIC/firmware burdenNot recommended for first build
High-Risk Unknowns
Compute Platform
  • Exact CM5 SKU is still needed: RAM, eMMC size, wireless/non-wireless.
  • CM5 gives useful USB, HDMI, MIPI, PCIe, GPIO/I2C/SPI/UART/I2S, and Ethernet PHY interfaces.
  • Main carrier input to CM5 is 5 V; design for up to 2.5 A CM5 peak plus all external loads.
  • Thermal solution and enclosure airflow/conduction path still matter.
  • Raspberry Pi OS/display support is lower risk than arbitrary RK3588 SOM BSP work.
Display / Keyboard
  • Display candidate is Waveshare 6.25inch DSI LCD (B): 720 x 1560, 2-lane Raspberry Pi-style MIPI DSI plus I2C Goodix touch.
  • CM5 is a strong fit because this display is documented for Raspberry Pi-style DSI overlays.
  • Remaining display risk is exact cable orientation, connector mapping, and whether the chosen CM5 DSI port/overlay setup is supported as intended.
  • Keyboard direction is now a custom PCB inspired by M5Stack CardKB dimensions and interface behavior.
  • CardKB reference is a 5 V I2C keyboard at address 0x5F, but a custom Linux cyberdeck keyboard should likely use USB HID unless always-on/wake behavior requires I2C or an embedded controller.
USB Topology
  • USB-C role must be defined.
  • Internal USB users may include LTE, keyboard/touch, RP2040, debug, and possibly display.
  • A USB hub may be required.
LTE/GNSS
  • SIM7600G-H-M.2 needs 3.3–4.2 V with 2 A-class burst capability.
  • Requires SIM/eSIM path, RF antennas, possible diversity antenna, GNSS active/passive antenna decision, and RF layout keepout.
LoRa
  • Frequency band and region must be selected.
  • Antenna location must be planned away from LTE, GNSS, display metalwork, and battery.
  • Decide whether RP2040 is controlled over USB, UART, or another interface.
Battery / Thermal
  • RK3588-class devices are not low-power microcontroller systems.
  • Battery and enclosure thermal path must be designed together.
  • USB-C PD is strongly recommended for a usable charge/run experience.
Minimum PCB Stackup Direction
  • SOM/SBC carrier with HDMI, USB 3.0, USB 2.0, RF, and multiple power rails: 6 layers recommended.
  • Raw RK3588S2 + LPDDR4x: 8+ layer HDI/microvia likely required.
Suggested Next Architecture Baseline
  1. Select the exact Raspberry Pi CM5 SKU.
  2. Use the Waveshare 6.25inch DSI LCD (B) after confirming CM5 DSI connector mapping, cable orientation, and overlay support.
  3. Design a custom keyboard PCB slightly longer than CardKB; default to USB HID plus optional wake/control lines.
  4. Use USB-C PD sink + charger/power path for the large tablet-style battery.
  5. Add USB hub if internal USB device count exceeds compute platform ports.
  6. Use external or enclosure-mounted RF antennas for LTE/GNSS/LoRa rather than relying on board-edge antennas buried inside metal/plastic near the display.
Information Needed From User
  • Preferred compute route: SBC, SOM carrier, or raw SoC.
  • Exact screen/keyboard model/manual/photos.
  • Battery chemistry/capacity/runtime target.
  • USB-C role and PD requirement.
  • HDMI role: internal, external, or both.
  • LoRa frequency region.
  • Antenna strategy.
  • Enclosure dimensions and cooling approach.

  • Summary Recommendation

  • Why Raw RK3588S2 + LPDDR4x Is Not Recommended

  • Practical Architecture Options

  • High-Risk Unknowns

  • Compute Platform

  • Display / Keyboard

  • USB Topology

  • LTE/GNSS

  • LoRa

  • Battery / Thermal

  • Minimum PCB Stackup Direction

  • Suggested Next Architecture Baseline

  • Information Needed From User