# Architecture and Cold-Power Design Study **Revision:** D **Status:** Phase 1A schematic architecture substantially captured; release remains blocked by authoritative OAM ball map, exact entry/fuse selections, ERC cleanup, and independent approval **Scope:** Deliverables A-E plus the Phase 1 schematic implementation and independent-review record below. PCB component placement and routing remain prohibited by ICD Article 10. ## Approved configuration baseline - **Slot Class A - frozen carrier target:** 1.5 kW nominal, 1.8 kW peak; one extended-temperature COM-HPC Server CPU module plus one OAM r2.0 accelerator. - **Slot Class B - backplane placeholder only:** 3 kW future dual-accelerator or higher-power slot. No Class B card-level design is authorized. The 48 V backplane and connector family shall scale through additional power blades or a double-width slot without changing the rack bus definition. - **CPU prototype baseline:** congatec conga-HPC/sILH industrial Xeon D class using an explicitly ordered -40 C Tcase SKU. - **Accelerator baseline:** vendor-agnostic OAM r2.0. Carry AMD Instinct-class and Intel Gaudi-class envelopes until selection. NVIDIA is outside this carrier scope except as a purchased vendor baseboard. - **Performance priority:** maximum sustained compute throughput and minimum host-to-accelerator latency. The management controller may limit performance for safety, but the carrier power tree shall not be the normal performance limiter. ## Executive decision Use a **48 V nominal card-cage bus** and a split Slot Class A carrier architecture: - A **COM-HPC Server Type Size D/E CPU module** receives a locally generated regulated 12 V rail. - A **48/54 V OCP Accelerator Module (OAM) r2.0** is the accelerator interface because it accepts the cage bus and supports up to 1000 W from 44-59.5 V.[OCP OAM r2.0](https://www.opencompute.org/documents/oai-oam-base-specification-r2-0-v1-0-20230919-pdf) AMD MI300X is a 750 W, 54 V OAM with PCIe Gen5 x16; Intel Gaudi 3 HL-325L is an OAM v2.0 module rated up to 900 W.[AMD MI300X](https://www.amd.com/en/products/accelerators/instinct/mi300/mi300x.html) [Intel Gaudi 3 HL-325L](https://cdrdv2-public.intel.com/817487/gaudi-3-ai-accelerator-hl-325l-oam-mezzanine-card-product-brief.pdf) - An always-on cold-rated supervisory controller owns hot-swap, warm admission, interlocks, coolant/plate telemetry, and release of compute power. - CPU and GPU module vendor power stages remain on their modules. The carrier does **not** recreate Intel socket VRs or an NVIDIA SXM/HGX baseboard unless a later program decision accepts proprietary documentation, validation, and schedule risk. The cold environment is used as design margin, not as an excuse to remove phases before characterization. Copper DC resistance is about **17.7% lower at -20 C** than at 25 C, but CPU/GPU transient response, connector limits, magnetics, control stability, and module warranties still govern the phase count. --- # A. System block diagram ```mermaid flowchart TD BP["Card-cage backplane\n48 V nominal bus\nmanagement and fabric"] --> PE["Power entry\nfuse and precharge\nhot-swap and telemetry"] PE --> BUS48["Protected 48 V payload bus"] PE --> AON["Always-on isolated housekeeping\n12 V AON, 5 V, 3.3 V"] BUS48 --> OAM["OCP OAM accelerator module\n48 V high-power input\nPCIe host link"] BUS48 --> IBC["48 V to regulated 12 V\nparallel intermediate bus converters"] IBC --> CPU["COM-HPC Server CPU module\n12 V and standby power"] IBC --> AUX12["12 V carrier loads\nstorage and fabric options"] CPU <-->|"PCIe Gen5 or vendor-qualified fabric"| OAM CPU --> NET["Backplane fabric\nEthernet or PCIe or CXL"] CPU --> STORAGE["Single boot NVMe\nno general storage expansion"] AON --> BMC["Supervisory BMC or safety MCU\nindependent of host CPU"] BMC --> HSW["Power sequencer and interlocks"] HSW --> PE HSW --> IBC HSW --> OAM HSW --> CPU SENS["Temperature network\nCPU module and GPU module\nVRMs, coolant in and out\nboard edge and cold plates"] --> BMC LEAK["Leak and condensation sensors\npressure and flow permissives"] --> BMC BP_MGMT["Backplane management\nredundant CAN or Ethernet\nplus discrete kill"] --> BMC COLD["Dual cold plates\ndie pedestals and VRM lands\ncompliant interface layers"] --- CPU COLD --- OAM COLD --- IBC ``` ## A1. Block responsibilities | Block | Responsibility | Architecture decision | |---|---|---| | Backplane interface | Blind-mate 48 V, protective earth/chassis first-mate, management, high-speed fabric | Separate high-current power blades from high-speed signal connectors; include mate-last/break-first presence or power-kill contact. OCP ORv3 connector families demonstrate 48 V, 100 A+ card interfaces with sense and chassis-ground contacts.[TE ORv3 power guide](https://www.te.com/content/dam/te-com/documents/datacomm/global/ocp-orv3-power-solutions-guide.pdf) | | Power entry | Fuse, reverse-energy control, inrush, current/power telemetry, fault isolation | A 10-80 V PMBus hot-swap controller such as **TI LM5066I** is a viable controller class, but the external MOSFET bank and fuse interrupt rating must be designed for the actual rack fault current.[TI LM5066I EVM](https://www.ti.com/tool/LM5066IEVM-626) | | CPU compute | Intel server-class CPU and memory | Prefer COM-HPC Server. PICMG describes two 400-pin connectors, up to 65 PCIe Gen5 lanes, fixed 12 V input, and up to 358 W module input.[PICMG COM-HPC](https://www.picmg.org/openstandards/com-hpc/) | | Accelerator | Vendor accelerator module | Use OAM r2.0 and carry AMD Instinct-class plus Intel Gaudi-class mechanical/power envelopes until selection. NVIDIA SXM/HGX remains outside this carrier and is reachable only through a purchased vendor baseboard. | | Interconnect | CPU-to-accelerator and backplane fabric | Baseline PCIe Gen5 x16. CXL is optional only if both chosen modules support the same revision and retimer topology. NVLink is not assumed available to a custom carrier. | | Management | Warm admission, telemetry, interlocks, logging, safe shutdown | Independent BMC/safety MCU powered from always-on rail. Hardware kill path remains functional without host firmware. | | Cooling mechanics | Clamp board/module stack between cold plates | Cold plates contact module-defined heat-spreader or pedestal zones and converter thermal lands; the PCB is not used as the primary heat spreader. | ## A2. Performance-first interconnect and stackup direction - Use a **Megtron-6-class ultra-low-loss family** for all PCIe Gen5 host routing, with HVLP copper and continuous ground references. The preferred baseline is Panasonic **MEGTRON6 R-5775(N)/R-5670(N)** or an electrically and mechanically equivalent material: Dk 3.34 and Df 0.0037 at 13 GHz, Tg 185 C, X/Y CTE 14-16 ppm/C, and Z-axis CTE 45 ppm/C below Tg.[Panasonic MEGTRON6](https://industrial.panasonic.com/ww/products/pt/megtron/megtron6) - A lower-CTE alternative for fabrication review is halogen-free MEGTRON6 **R-5375(N)**, with Df 0.0029 at 13 GHz and Z-axis CTE 39 ppm/C. It is preferred if the selected fabricator can control impedance and reliability with the material.[Panasonic HF MEGTRON6](https://industrial.panasonic.com/content/data/EM/PDF/DataS_Hf-MEGTRON6_R-5375_en_202407.pdf) - Plan a **14-18 copper-layer family**, not a generic 6- or 8-layer server board: at least four solid ground reference planes, dedicated 48 V and 12 V distribution layers, local low-voltage planes, and paired stripline layers for PCIe Gen5 and module high-speed escape. Exact count waits for module pin maps and fabricator field-solver results. - Target PCIe Gen5 at **85 ohm differential**, broadside or edge-coupled stripline with no plane splits, back-drilled through vias, and matched via structures. Final geometry is fabrication-specific; no width/spacing is frozen yet. - Eliminate the retimer by placing the COM-HPC PCIe root-complex connector edge directly opposite the OAM host-link connector, with the x16 lane field facing inward. Use one direct baseboard segment, no riser, no cable, no intermediate connector, and no layer transition except those required for module escape. - Set a provisional **root-connector to OAM-connector routed-length goal <=100 mm**, with a hard review at 125 mm. PCI-SIG gives a 36 dB end-to-end Gen5 budget and about 16 dB for the system board; low-loss material is commonly used when routes exceed roughly 10 inches, but this carrier targets a much shorter direct path.[PCI-SIG Gen5 implementation](https://pcisig.com/sites/default/files/files/PCI-SIG-Seamless_Transition_to_PCIe_5.0_in_System_Implementations_FINAL.pdf) - A retimer is added only if correlated channel simulation and later measurement fail the PCIe Gen5 eye/loss criteria. It is **not** included in the baseline BOM because it adds latency, power, software dependencies, thermal load, and two additional electrical segments. ## A3. Memory and sustained-performance intent - DDR5 remains entirely on the COM-HPC module. Select the module/DIMM option with the shortest vendor-supported topology, preferably one DIMM per channel and no carrier-level memory connector or buffer. - The Class A power tree is sized so 1.5 kW can be sustained continuously and the 1.8 kW envelope can be supported for the selected module excursion duration without rail droop or thermal throttling. - Cold plates must cover CPU, OAM, module VRMs, and 48-to-12 V conversion surfaces. Maximum boost is permitted only while all rail, plate, coolant, and module temperatures stay inside validated bounds. - Decoupling is divided by frequency: module-local high-frequency MLCCs, carrier connector-side ceramic/polymer banks, and controlled 48 V energy storage behind hot-swap. Exact capacitance follows the selected module impedance and excursion specifications. - The management controller commands platform power/performance states and logs margin. Its default state is unrestricted performance after warm admission; it throttles only for a measured safety or power-envelope condition. ## A4. Deleted non-compute passengers - All legacy display, audio, PS/2, LPC expansion, serial-port user interfaces, parallel I/O, and general-purpose USB front-panel functions. - Discrete peripheral controllers already reachable through the backplane management network. - Extra SATA controllers, RAID functions, multiple local NVMe devices, removable media, and general local storage expansion. - On-card front-panel user interface beyond service/debug status required for bring-up. - Carrier Ethernet NICs not required for the selected backplane fabric or management path. - Baseline local storage is **one NVMe boot device only**. ## A5. Warm-admission sequence 1. **Insertion/off state:** only the protected always-on supply starts. Main 48 V payload remains disabled. 2. **Validate enclosure:** dry-nitrogen pressure/purity indication, no leak/condensation alarm, coolant flow present, inlet/outlet sensors plausible, cold plates mechanically present. 3. **Warm-soak requirement:** all boot-critical module and local-board sensors must be **at least +5 C**, with a recommended release threshold of +7 C and 2 C hysteresis. External heaters or warm coolant are chassis functions; the carrier only commands and verifies them. 4. **Enable protected 48 V payload**, then 48-to-12 V conversion and standby rails. 5. **Release CPU module reset/power enable**, verify module management/telemetry, then enumerate the accelerator. 6. **Permit cooling ramp:** supervisory controller authorizes coolant setpoint reduction in bounded steps while checking temperature rate-of-change, minimum component temperatures, rail margins, and clock/PCIe error counters. 7. **Run at -20 C:** any sensor below the validated operating floor, telemetry loss, loss of flow, leak indication, or abnormal rail excursion triggers workload throttle, controlled shutdown, then payload isolation. 8. **-40 C excursion:** study/qualification mode only until every module, connector, capacitor, oscillator, laminate stack, TIM, and coating process is qualified. ## A6. Thermal-mechanical concept - Use **two structural cold plates tied together by perimeter through-bolts**, so clamp force closes through metal spacers/standoffs rather than through unsupported PCB areas. - Establish a **perimeter stiffener frame** plus local metallic load-spreader frames around the COM-HPC and OAM connectors. Avoid applying pedestal load directly through mezzanine connectors. - Initial study pattern: perimeter bosses at approximately 40-60 mm spacing, additional bosses adjacent to each long edge of both compute modules, and symmetric support around each die pedestal. Exact coordinates wait for selected modules and plate FEA. - Each die-area pedestal needs a compliant, replaceable thermal interface and a hard mechanical stop that limits compression. Parallelism, flatness, and connector-stack tolerance must be analyzed together. - Place telemetry at: each 48-to-12 V converter bank, each module power-entry region, CPU heat-spreader/pedestal edge, GPU/OAM pedestal edge, coolant inlet, coolant outlet, both plate edge regions, card leading edge, backplane connector region, and one board-center reference. - Candidate local sensor classes include **TMP175** (-40 to 125 C, I2C/SMBus, 27 addresses) and **MAX31875** (-50 to 150 C); final selection depends on package assembly capability and required absolute accuracy.[TI TMP175](https://www.ti.com/product/TMP175) [ADI MAX31875](https://www.analog.com/en/products/max31875.html) ## A7. Air-cooling rules explicitly deleted - No fans, fan headers, tach/PWM fan control, fan-failure logic, or fan service clearances. - No front-to-back airflow corridor, DIMM airflow spacing rule, heatsink-fin keepout, or air-baffle geometry. - No reliance on convective cooling for any power component. - Component keepouts are instead driven by cold-plate pedestals, compliant gap pads, clamping hardware, dielectric clearances, service extraction, coating masks, and high-speed routing. - Airflow-derived connector/VRM placement is deleted; thermal placement follows cold-plate contact and short electrical paths. --- # B. VRM and power subsystem study ## B1. Preliminary power budget This is an architecture budget, not a selected-module guarantee. | Load | Nominal design allocation | Peak/excursion allocation | Delivery path | |---|---:|---:|---| | OAM GPU/accelerator | 750-900 W candidate range | 1000 W interface ceiling; module-specific peak TBD | Protected 48 V directly to module | | COM-HPC CPU module | 300 W | 358 W connector limit | 48 V to regulated 12 V | | Storage/network/fabric | 150 W | 250 W | 48 V to 12 V and local PoL | | Management, telemetry, losses | 50 W | 100 W | Always-on and auxiliary rails | | **Slot Class A total** | **1500 W** | **1800 W** | Frozen carrier envelope | | **Slot Class B placeholder** | **3000 W** | **TBD** | Backplane/connector scalability only; no card design | The Class A card is intentionally capped at 1.5 kW nominal and 1.8 kW peak. Class B is not a stuffed option of this PCB; it is a future double-width or increased-blade-count slot using the same 48 V backplane standard. ## B2. Recommended conversion topology - **48 V directly to OAM** where the selected accelerator supports the OAM high-power input. - **48 V to regulated 12 V** for COM-HPC and legacy 12 V loads using parallel, conduction-cooled converter modules. Current commercial examples include Vicor DCM products up to 2 kW at up to 96.5% peak efficiency and NBM products up to 2.4 kW above 98% peak efficiency.[Vicor 12V/48V conversion](https://www.vicorpower.com/industries-and-innovations/vicor-48v/12v-48v-conversion) - For a development carrier, use converter modules rather than a custom kilowatt-class discrete converter. They shorten validation and put a characterized thermal surface against the cold plate. - Generate 5 V, 3.3 V, 1.8 V, and management rails from the protected 12 V or always-on supply with industrial-temperature PoL converters. - If a full custom Intel socket board is later chosen, use the processor-generation-specific Intel SVID controller and smart power stages. Example controller classes include Infineon **XDPE1B2C4B** (dual-loop 12-phase, Intel VR13/VR14) and onsemi **FD5012** (12-phase Intel SVID). These examples do not prove compatibility with an unselected CPU generation.[Infineon XDPE1B2C4B](https://www.infineon.com/part/XDPE1B2C4B-0000) [onsemi FD5012](https://www.onsemi.com/products/power-management/dc-dc-power-conversion/controllers/fd5012mntxg) ## B3. 25 C versus cold copper calculation Using copper's standard near-room-temperature resistance coefficient, alpha = 0.00393/C: `R(T) / R(25 C) = 1 + alpha x (T - 25 C)` | Copper temperature | Resistance ratio vs 25 C | I2R loss reduction, same geometry | Copper cross-section giving same DC resistance as 25 C baseline | |---:|---:|---:|---:| | +25 C | 1.000 | 0% | 100% | | -20 C | 0.823 | **17.7%** | **82.3%** | | -40 C | 0.745 | **25.5%** | **74.5%** | ### What this permits - A plane or busbar that is loss-limited only by copper DC resistance could theoretically use about **17.7% less copper cross-section at -20 C** for the same loss as the +25 C baseline. - Conversely, retaining the baseline copper yields 17.7% lower conductor loss and more transient/thermal margin. ### Design decision Do **not** reduce the main power copper by the full theoretical amount. Use only half the calculated benefit as a design credit until thermal cycling and current-distribution tests are complete: - **Study credit at -20 C:** maximum **8% reduction** in copper cross-section versus the 25 C loss-based design. - **Recommended first prototype:** retain the full 25 C copper design. Treat the 17.7% reduction as efficiency and reliability margin. - Connector contacts, vias, neck-downs, local hot spots, and fault current do not receive the same blanket reduction. ## B4. Phase-count comparison | Subsystem | 25 C baseline | -20 C preliminary | Explicit saving | |---|---:|---:|---:| | COM-HPC on-module CPU VR | Defined by module vendor | Unchanged | **0 phases** | | OAM on-module accelerator VR | Defined by module vendor | Unchanged | **0 phases** | | Carrier 48-to-12 V converter array | Size to N+1 or required derating | Same module count initially | **0 converter phases/modules** | | Custom socket VR, if pursued | CPU-generation load-line and transient calculation | Same initial count; later characterize | **0 phases claimed** | This is deliberate. Lower copper resistance and potentially lower MOSFET Rds(on) reduce conduction loss, but they do not remove the requirements for peak phase current, inductor saturation margin, load-step response, output ripple, fault tolerance, or vendor VR specifications. Any phase reduction must be demonstrated with the exact smart power stage, inductor, controller compensation, and cold load-step waveform. No generic MOSFET cold saving is claimed because it is part-specific. ## B5. Example 48-to-12 V sizing At 96% conversion efficiency: | 12 V output power | 12 V output current | 48 V input current | Practical converter approach | |---:|---:|---:|---| | 358 W COM-HPC maximum input | 29.8 A | 7.8 A | One >=500 W regulated module, or two smaller modules for redundancy | | 750 W auxiliary domain | 62.5 A | 16.3 A | One 750 W/1 kW module or paralleled modules | | 1500 W 12 V domain | 125 A | 32.6 A | Two 1 kW modules with derating/current sharing | | 3000 W all converted to 12 V | 250 A | 65.1 A | Not recommended; preserve 48 V delivery to accelerators | The architecture avoids converting the accelerator power to 12 V, which prevents hundreds of amperes from crossing the carrier. --- # C. Cold-rated BOM philosophy | Component class | Standard server practice | Cold-native replacement or rule | Example/source | Why | |---|---|---|---|---| | CPU module | Commercial socketed motherboard | COM-HPC Server module with vendor-rated extended-temperature SKU | congatec conga-HPC/sILH lists selected Xeon D variants with -40 C minimum Tcase; commercial variants list 0 C minimum.[conga-HPC/sILH guide](https://www.congatec.com/fileadmin/user_upload/Documents/Manual/HEIH.pdf) | Keeps socket, memory topology, BIOS, and high-current CPU VR on a qualified module. | | Accelerator | Custom NVIDIA SXM baseboard | Public OAM module first; NVIDIA SXM/HGX only through qualified vendor platform agreement | OAM r2.0: 44-59.5 V, up to 1000 W; 102 x 170 mm; Molex Mirror Mezz Pro 218910-1115 or 218916-1115.[OAM r2.0](https://www.opencompute.org/documents/oai-oam-base-specification-r2-0-v1-0-20230919-pdf) | Avoids proprietary SXM electrical/mechanical implementation and aligns with 48 V. | | Bulk capacitors | Liquid aluminum electrolytic | Conductive-polymer aluminum, polymer tantalum where appropriate, film, and MLCC arrays | Panasonic OS-CON families; exact series/MPN must show category minimum <= -40 C.[Panasonic OS-CON](https://industrial.panasonic.com/ww/products/pt/os-con/lineup) | Avoids electrolyte viscosity/ESR problems; lower ESR and better cold behavior. | | MLCC | X5R/X7R selected only for room-temperature nominal capacitance | X7R/X8R or C0G/NP0; verify capacitance across DC bias and -40 C; use 2x nominal design allowance minimum | Vendor-specific impedance/capacitance curves required | Temperature class alone does not cover DC-bias loss, board flex, or cryogenic behavior. | | Precision timing | Bare crystal relying on IC oscillator | TCXO or qualified XO with -40 C or lower rating | IQD **IQXT-210-47 / LFTCXO085791**: -40 to 105 C TCXO. CTS **CA25C** is an XO, not TCXO, rated to -55 C.[IQXT-210-47 data](https://www.ariat-tech.com/datasheet/07/LFTCXO085791.pdf) [CTS CA25C](https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Clock-Oscillators/clock-ocillators-CA25C-datasheet.pdf) | Controls frequency drift through the warm-to-cold transition. Exact frequency/jitter must match the chosen module/interface. | | RTC backup | CR2032 coin cell on carrier | Prefer backplane-powered always-on RTC; otherwise a -40 C supercapacitor for short hold-up or relocate battery to warm service area | Eaton **KW-5R5C224-R** family: 5.5 V, -40 to 85 C, RTC backup.[Eaton KW datasheet](https://www.eaton.com/content/dam/eaton/products/electronic-components/resources/data-sheet/eaton-kw-supercapacitors-coin-cells-data-sheet.pdf) | Common coin cells have poor cold capacity/impedance and create service risk in a sealed enclosure. | | Hot-swap controller | 12 V eFuse/hot-swap | 80 V-class controller with external FETs, PMBus telemetry, cold-rated passives | TI **LM5066I**, 10-80 V controller; temperature rating must be confirmed from the ordering datasheet before release.[TI LM5066I](https://www.ti.com/tool/LM5066IEVM-626) | Supports live insertion at 48 V and reports energy/current/power. | | 48-to-12 V conversion | Discrete motherboard converter | Conduction-cooled high-density module, paralleled as required | Vicor **DCM3717S60D13K0TN1** 1 kW or **DCM3735S60D13L0TN1** 2 kW product direction; exact production status and temperature grade require procurement verification.[Vicor product announcement](https://www.newelectronics.co.uk/content/product-launches/vicor-releases-family-of-regulated-48v-to-12v-dcm-dc-dc-converters) | Reduces development risk and creates defined cold-plate surfaces. | | Temperature sensors | Few ambient sensors optimized for airflow | Distributed I2C/SMBus sensors plus module telemetry and redundant analog trips | TI **TMP175** (-40 to 125 C), ADI **MAX31875** (-50 to 150 C) | Detects gradients because there is no mixing airflow. | | Power connector | ATX/EPS cable headers | Blind-mate 48 V busbar connector with early chassis ground and mate-last sense | TE ORv3 IT Gear family, including 2389779 variants; up to 100 A/150 A+ family options.[TE ORv3](https://www.te.com/content/dam/te-com/documents/datacomm/global/ocp-orv3-power-solutions-guide.pdf) | Lower current, controlled hot-plug sequence, and mechanical float. | | High-speed connectors | Consumer/commercial connector by geometry only | Vendor series explicitly rated to -40 C after full mated-stack review | Amphenol Minitek Pwr CEM-5 auxiliary connector operates -40 to 105 C; signal mezzanine and PCIe connector MPNs remain open.[Amphenol CEM-5](https://atta.szlcsc.com/upload/public/pdf/source/20240807/D083D39648550B55B13CADE514B8D803.pdf) | Plastic, plating, contact force, and differential geometry all need cold-cycle qualification. | | Laminate | Generic FR-4 | Megtron-6-class low-loss, low-CTE multilayer family with HVLP copper and spread/low-Dk glass | Preferred: Panasonic **R-5775(N)/R-5670(N)**; alternate **R-5375(N)** if fabricator-qualified. Df 0.0037 or 0.0029 at 13 GHz; Z CTE 45 or 39 ppm/C respectively.[MEGTRON6](https://industrial.panasonic.com/ww/products/pt/megtron/megtron6) [HF MEGTRON6](https://industrial.panasonic.com/content/data/EM/PDF/DataS_Hf-MEGTRON6_R-5375_en_202407.pdf) | Meets Gen5 loss intent while keeping Z-axis CTE comparable to high-reliability server laminates. Low-temperature coupons remain mandatory. | | Conformal coating | Acrylic coating selected mainly for moisture | Low-modulus silicone with verified thermal shock, masked connectors and thermal interfaces | HumiSeal **1C49LVF**: thermal shock -65 to 200 C, Tg below -65 C; DOWSIL **3-1965** is another low-stress silicone class.[HumiSeal 1C49LVF](https://cdnresources.chasecorp.com/7RYJKHTS/at/398cq6xkrjbxhmsqvthpzhm/1C49LV_HumiSeal_Technical_Data_Sheet.pdf) [DOWSIL 3-1965](https://www.conro.com/downloads/Manuals/Dowsil-3-1965-Conformal-Coating-18-1kg-Pail-TDS.pdf) | Flexible coating better accommodates differential contraction than a stiff film. Compatibility testing remains mandatory. | | Thermal interface | Room-temperature pad/grease chosen from conductivity only | Low-temperature compliant pad/grease with pump-out and compression-set data | No MPN selected | Must preserve contact through -40 to warm cycling and clamp relaxation. | | Inductors | Rated by current and hot-temperature rise | Ferrite/core-loss and inductance verified at -40 C, saturation at worst current, mechanically bonded for cycling | No MPN selected | Permeability and adhesive/mechanical behavior can change at cold. | | Resistors/shunts | Standard thick-film | Metal-element shunts with low TCR and Kelvin sense; thin-film precision networks for thresholds | No MPN selected | Warm-to-cold drift directly changes current limits and admission thresholds. | | Solder/assembly | Standard server PCBA | Lead-free alloy and BGA/land pattern validated by thermal-cycle coupons; underfill only where rework and CTE analysis permit | Process qualification required | The dominant reliability risk is repeated CTE strain, not steady cold operation alone. | --- # D. Assumptions requiring validation 1. **Exact CPU module is not selected.** COM-HPC is the approved architecture direction, but only specifically ordered extended-temperature module/SKU combinations may be operated below 0 C. 2. **Intel warm admission is a system policy, not proof of below-spec qualification.** Starting above +5 C does not itself authorize a commercial CPU/module to continue at -20 C. Written vendor approval or qualification testing is required. 3. **Exact OAM accelerator is not selected.** Carry AMD Instinct-class and Intel Gaudi-class envelopes; confirm vendor availability, firmware, cold-plate interface, and qualification support. 4. **NVIDIA is not a baseline accelerator candidate.** Any later NVIDIA path uses a purchased vendor baseboard outside this carrier scope. 5. **Slot Class B is not a card requirement.** The 3 kW placeholder applies only to backplane and connector-family scalability; the Class A card, fuse, hot-swap stage, and clamps are sized only for 1.5 kW nominal and 1.8 kW peak. 6. **GPU and CPU power excursions are placeholders.** Obtain module-vendor EDP/transient profiles, durations, and power-brake behavior. 7. **No MOSFET Rds(on) cold percentage is claimed.** Characterize the exact hot-swap FETs, converter power stages, and smart stages from -40 C through hot junction conditions. 8. **No phase-count reduction is claimed.** The user-requested comparison currently yields zero safe phase savings; revisit only after cold load-step testing. 9. **The copper calculation assumes uniform copper temperature.** Local copper near silicon, converter modules, connectors, and cold-plate interfaces may be substantially warmer than -20 C. 10. **The -40 C case is a study excursion, not yet an operating point.** Every critical part and material needs an explicit -40 C rating or qualification plan. 11. **COM-HPC connector cold rating is unverified here.** Obtain the exact Samtec AcceleRate HP series part numbers and written operating-temperature limits for the chosen stack height. 12. **OAM Mirror Mezz connector cold rating is unverified here.** Molex 218910-1115/218916-1115 geometry is specified by OAM, but temperature, plating, and cycle-life confirmation is required. 13. **Backplane power connector MPN is not frozen.** Choose the exact ORv3-style part by card current, available float, insertion force, cage geometry, and -40 C rating. 14. **PCIe/CXL channel architecture is not closed.** Lane count, generation, retimers, connector topology, and total insertion-loss budget depend on selected CPU/OAM modules and backplane length. 15. **NVLink is excluded unless NVIDIA supplies an approved platform design.** PCIe is the baseline host link. 16. **TCXO frequency and jitter are not selected.** IQXT-210-47 is evidence that a -40 C TCXO class exists, not a final clock choice. 17. **RTC hold-up duration is not specified.** Eaton KW supercapacitors support -40 C but may provide only hours/days depending on RTC current; use backplane standby or relocate the energy source if longer retention is required. 18. **Panasonic polymer series minimum temperature must be verified per exact MPN.** Family-level low-temperature behavior is not enough for AVL release. 19. **MLCC cold and DC-bias capacitance remains unverified per MPN.** Validate at actual rail voltage, mechanical strain, frequency, and -40 C. 20. **Laminate datasheets emphasize high-temperature properties.** Low-temperature CTE, dielectric behavior, and microvia/PTH reliability need stackup coupons and thermal cycling. 21. **Conformal coating compatibility is not proven.** Test adhesion, trapped contamination, connector masking, TIM interaction, rework, and thermal cycling on the actual assembly. 22. **Dry nitrogen does not eliminate condensation during service or warm admission.** Define dew point, purge procedure, moisture sensing, door-open recovery, and coolant leak detection. 23. **Warm-up method is off-board and undefined.** Chassis heater capacity or warm-coolant control must bring every boot-critical component above threshold without excessive gradients. 24. **Cold-plate force and boss spacing are conceptual.** Final pattern requires module mechanical drawings, connector compression limits, PCB thickness, stiffener design, TIM compression curve, and FEA. 25. **Cold-plate electrical isolation is undefined.** Determine chassis bonding, dielectric TIM requirements, creepage, and fault-current path. 26. **Coolant chemistry and material compatibility are undefined.** Confirm seals, plate alloy, galvanic couples, conductivity, viscosity at -40 C, and leak-detection method. 27. **Hot-swap SOA is not sized.** Rack source impedance, maximum prospective fault current, input capacitance, insertion bounce, and required ride-through are missing. 28. **Fuse interrupt rating is not sized.** It must exceed the maximum available current from the centralized bus at the nearest slot. 29. **Bus hold-up and redundancy are undefined.** Determine single-feed versus A/B feed, ride-through time, and whether the card must survive source transfer. 30. **Management controller selection is open.** It must start reliably at -40 C even though compute admission waits for +5 C, and it must support an independent hardware shutdown path. 31. **Sensor accuracy below 0 C must be budgeted.** Include IC accuracy, board gradients, sensor attachment, calibration, and telemetry bus faults. 32. **Module firmware behavior during cooling is unverified.** Validate PECI/DTS, GPU telemetry, PCIe links, DRAM, clocks, and error handling through the full temperature ramp. 33. **Commercial DIMMs/SSDs/NICs may be the limiting cold-rated components.** Prefer soldered/industrial memory where the module supports it, or obtain extended-temperature options. 34. **Vertical extraction loads are undefined.** Card guides, handles, blind-mate forces, cold-line couplings, and plate mass must be included in the chassis mechanical design. 35. **Conduction-only cooling applies to all components.** Any component lacking a defined plate contact or board-conduction path must be thermally modeled and instrumented. 36. **AMD MI300X and Intel Gaudi 3 are envelope candidates, not interchangeable qualified modules.** Their exact OAM revision, keepouts, management, cold-plate interface, firmware, and procurement path must be confirmed. 37. **Gaudi 3 can consume most of the Class A accelerator allocation.** A 900 W module leaves about 600 W nominal for CPU, conversion loss, boot NVMe, management, and fabric; close the detailed budget before selection. 38. **The no-retimer topology is provisional.** Validate package, connector, via, trace, and crosstalk models with a correlated PCIe Gen5 channel simulation and 10-20% loss margin. 39. **The <=100 mm Gen5 route goal depends on mechanical feasibility.** Module connector orientation, cold-plate pedestals, stiffeners, service extraction, and minimum bend/escape geometry may force a longer path. 40. **Cold dielectric behavior is not characterized by the room-temperature laminate values cited.** Measure or obtain Dk/Df versus temperature and include -40 C coupons in channel correlation. 41. **DDR5 remains vendor-controlled on the CPU module.** Confirm the selected module, DIMMs, SPD/PMICs, and topology operate through the -20 C run condition and -40 C study excursion. 42. **Sustained maximum boost requires module-vendor permission.** TDP, cTDP, power-limit timers, current excursions, and thermal-control firmware must allow indefinite operation at the intended power state. 43. **The 1.8 kW peak duration is not defined.** Freeze duration and repetition rate from CPU/OAM excursion specifications before sizing hot-swap SOA, connector heating, bulk capacitance, and coolant transient response. 44. **Decoupling remains un-sized.** Obtain module input-impedance limits, allowed voltage droop, source inductance, and power-excursion waveforms before selecting polymer/MLCC quantities. 45. **Backplane Class B scaling is mechanical as well as electrical.** Verify additional blade count or double-width slot geometry, cage keying, extraction force, and busbar fault-current coordination. --- # E. Bus voltage recommendation ## E1. Current comparison Ignoring conversion loss for the simple backplane comparison: | Board power | 12 V bus | 48 V bus | 80 V bus | 380 V bus | |---:|---:|---:|---:|---:| | 1 kW | 83.3 A | 20.8 A | 12.5 A | 2.63 A | | 1.5 kW | 125 A | 31.3 A | 18.8 A | 3.95 A | | 3 kW | 250 A | 62.5 A | 37.5 A | 7.89 A | For the same conductor resistance and delivered power, distribution loss scales with `1 / V^2`: - 12 V has **16x** the I2R loss of 48 V. - 48 V has **2.78x** the I2R loss of 80 V. - 48 V has **62.7x** the I2R loss of 380 V, but 380 V moves conversion, insulation, arc, service, and regulatory burden onto every removable card. Cold copper reduces each option's conductor loss by the same approximate percentage; it does not change the voltage ranking. ## E2. Option assessment ### 12 V legacy **Reject for the cage bus.** - 83-250 A per card at 1-3 kW creates large connector, busbar, plane, and fault-current burdens. - It remains useful as the local COM-HPC intermediate bus because COM-HPC Server modules are defined around fixed 12 V input. - A 12 V cage would force high-power OAM operation onto the lower-power 350 W profile or require a large carrier conversion stage. ### 48 V nominal, OCP-style **Recommended.** - 20.8-62.5 A per card over the stated power range is practical with blind-mate busbar connectors. - OAM directly supports 44-59.5 V high-power input, avoiding an unnecessary accelerator conversion stage. - COM-HPC is served through one localized 48-to-12 V stage. - Commercial 48 V hot-swap controllers, telemetry devices, converters, and OCP mechanical ecosystems exist. TE's ORv3 family targets 48 V and 100 A+ IT gear connections; OCP specifications include live-insertion/power-kill practices.[TE ORv3](https://www.te.com/content/dam/te-com/documents/datacomm/global/ocp-orv3-power-solutions-guide.pdf) - Keep the normal operating maximum at or below the selected OAM and connector rating. A 54 V nominal plant with transients must be coordinated against the OAM 59.5/60 V ceiling and hot-swap/TVS limits. ### 72-80 V intermediate distribution **Not recommended for the first architecture.** - Current drops relative to 48 V, but the bus no longer directly matches OAM's 44-59.5 V input. - Every accelerator needs a high-power conversion stage, erasing much of the system simplicity. - Crossing common 60 V DC touch-safety boundaries increases connector, service, insulation, and compliance obligations. - The commercial data-center hot-swap and module ecosystem is thinner than 48 V. ### 380-400 V DC **Reject at removable-card level; consider only at rack power-shelf level.** - Excellent current reduction, but hazardous-voltage requirements, arcing, larger creepage/clearance, precharge, discharge, service interlocks, and isolation become card-level concerns. - Conversion must be isolated and highly protected on every card or at an intermediate shelf. - If facility distribution is high-voltage DC, convert centrally to a protected 48 V cage bus. ## E3. Recommended bus definition for the next phase - **Nominal:** 48 V DC rack/card-cage bus. - **Module compatibility target:** support OAM's 44-59.5 V input window, subject to exact module limits. - **Slot Class A card interface:** size for at least 45 A continuous at the 44 V low-line condition, then apply the selected connector's temperature, contact-count, coating, and lifecycle derating. The raw 1.8 kW low-line current is 40.9 A. - **Slot Class B backplane placeholder:** reserve a connector-family path to approximately 70 A through additional blades or a double-width slot, but do not install or size Class B hardware on the Class A card. - **Interface:** separate positive/return power blades, protective chassis contact that mates first/breaks last, presence/power-kill contact that mates last/breaks first, and independent management connector or contacts. - **Protection:** slot/source fuse coordination plus card hot-swap, UV/OV, inrush limiting, reverse-energy blocking as required, PMBus telemetry, and hardware kill. - **Conversion:** direct 48 V to OAM; regulated 12 V only for COM-HPC and legacy auxiliaries. --- # Approval checkpoint ## Phase 1 schematic implementation record — 2026-09-20 ### Implemented - Added real Flux-library components for the COM-HPC and provisional Mirror Mezz interfaces, reverse-blocking stage, 48 V pass-FET bank, always-on isolated 12 V converter, 5 V and 3.3 V management rails, STM32H563 management MCU, independent watchdog, CAN transceiver, I2C mux/buffer, six TMP175 sensors, and independent analog admission comparator/reference. - Wired reverse protection, the isolated AON supply, datasheet-backed TPS62177 3.3 V application, datasheet-backed TPSM63603 5 V application, MCU supply/VCAP/reset, watchdog, CAN PHY, segmented sensor buses, and the analog admission skeleton. - Named and annotated 48 V, 12 V AON, 5 V AON, 3.3 V AON, CAN, watchdog, sensor, and hardware-admission nets. Unselected hot-swap-control and analog-envelope inputs are explicitly named as pending rather than guessed. - Marked unused MCU pins as no-connect. **Independent inspection found that a default 160 × 100 mm, 4-layer PCB with the 59 footprints placed and 228 airwires exists. This conflicts with ICD Article 10 and supersedes the earlier no-PCB-mutation assertion. No copper routing was found.** ### Power budget used for schematic annotation | Domain | Basis | Annotated limit | |---|---:|---:| | Raw/protected 48 V Class A path | 1.8 kW / 44 V = 40.9 A, with margin | 45 A | | 12 V AON | URB4812YMD-20WR3 rating | 20 W / 1.67 A | | 5 V AON | TPSM63603 capability | 3 A maximum device capability; actual load lower | | 3.3 V AON | TPS62177 capability | 0.5 A | ### Parts instantiated and status | Function | Part | Status | |---|---|---| | COM-HPC interface | Amphenol 10163479-14340T1LF | Real library part; exact carrier pin map still required | | OAM interface | TE 203456-0003 | Provisional cold-rated Mirror Mezz family part; not the exact OAM 218910/218916 specified family | | Reverse blocking | LTC4359IDCB#TRMPBF + CSD19536KCS | Industrial-temperature controller variant; final FET orientation, SOA and gate network require review | | 48 V hot-swap controller | LM5066IPMHE/NOPB desired | BLOCKED: exact suitable part is not available in the Flux library; no lower-voltage substitute was used | | Hot-swap FET bank | 4 × PSMN4R8-100BSEJ | Provisional topology only; current sharing and SOA not closed | | Main 48-to-12 V CPU conversion | Vicor DCM3717S60D13K0TN1 direction | BLOCKED: exact module absent from Flux library; not substituted with an undersized part | | Always-on isolated supply | URB4812YMD-20WR3 | Implemented | | Management MCU | STM32H563ZIT6 | Implemented with internal oscillators; external TCXO remains selection-pending | | Management buses | TCA4307 + TCA9548A | Implemented; galvanic PMBus/I2C isolation remains open | | Sensors | 6 × TMP175AIDGKR | Implemented at entry, OAM, CPU converter A/B, COM-HPC and ambient locations | ### Explicit unresolved assumptions and conflicts 46. The exact COM-HPC carrier pin assignment is not present in the governing inputs; J1 remains electrically unmapped and therefore produces connector-pin ERC findings. 47. The exact OAM 218910/218916 connector part and public pin map are not available in the Flux library. J2 is a provisional family part and remains electrically unmapped. 48. LM5066IPMHE/NOPB is verified as active, 10–80 V, 28-pin PWP and −40 to +125 °C, but cannot be instantiated from the current Flux library. LTC4282 and ADM1278 are rejected as voltage-incompatible substitutes. 49. Hot-swap sense resistance, current limit, timer, power-limit resistor, FET SOA, fuse interrupt rating, input capacitance, insertion bounce and rack fault current are not closed. The present pass-FET bank is architectural only. 50. The available TVS 5.0SMDJ60A is provisional and conflicts with the 59.5 V OAM ceiling because its clamp is approximately 96.8 V. A coordinated bus-transient strategy is required before release. 51. The Vicor DCM3717 CPU converter and its parallel/current-share implementation are not instantiated because the exact module is absent from the library. 52. CPU/OAM enable, reset, presence, power-brake, PCIe, JTAG, firmware-update, leak, flow and backplane-kill assignments remain blocked by module/interface pin maps. 53. CAN_H and CAN_L and the analog cold-permissive input intentionally terminate at named interface portals and therefore remain single-pin-net ERC findings until interface pins are selected. 54. AON_GND is presently isolated from chassis/payload GND by design intent. The required bonding, isolation barrier and fault-current strategy remain to be approved. 55. The TPSM63603 5 V rail is wired to a datasheet 5 V/1 MHz application; thermal and load derating at the cold-plate operating condition remain to be verified. 56. The STM32 FDCAN2 PB5/PB6 and I2C PB8/PB9 assignments are based on datasheet alternate-function evidence but remain subject to firmware/pin-map review. ### Verification status - Read-back inspection confirms the project contains the named power and management nets and the implemented component set. - ERC remains open primarily because both high-pin-count module connectors are intentionally unmapped, the hot-swap controller and main Vicor modules are unavailable, and three selection-pending interface nets terminate at portals. - This is not a release-ready or ERC-clean schematic. The architecture is preserved without inventing missing connector mappings or substituting voltage-incompatible parts. ### Independent review findings The Phase 1 checkpoint is **not approved**. Blocking errors are: missing blind-mate entry connector/fuse/80 V PMBus hot-swap controller and its UV/OV/inrush/current-sense circuitry; unresolved TVS coordination; absent N+1 48-to-12 V converter bank; only one management CAN channel; no firmware-independent payload kill; incomplete +5/+7 C hysteretic admission/permissive logic; incomplete Article 7 sensor coverage and analog redundancy; one COM-HPC connector instead of the required pair; provisional non-OAM J2; absent module power/control/PCIe stubs; and absence of the required literal `ENVELOPE-PENDING-SELECTION` net token. Review also found missing cold evidence for multiple parts and approximately 1,102 ERC errors dominated by unmapped connector pins. 57. The automatically created 160 × 100 mm, 4-layer PCB and placed footprints conflict with ICD Article 10. The PCB state must be removed or explicitly reverted without losing the schematic before any approval claim. 58. Phase 1 requires authoritative COM-HPC Server carrier pin maps for both 400-pin connectors and the OAM r2.0 Mirror Mezz pin map before interface stubs can be completed and unused pins intentionally marked. 59. The present capture has no acceptable 80 V PMBus hot-swap controller or N+1 main converter implementation. Exact real parts must be sourced/imported/created from manufacturer datasheets; voltage-incompatible substitutions remain prohibited. 60. The present 5.0SMDJ60A transient clamp is architecturally incompatible with the 59.5 V OAM ceiling until a system-level source clamp/TVS/OV shutdown coordination study proves otherwise; it is not approved for release. 61. Article 7 telemetry requires additional digital sensor locations, redundant analog trip channels, and bus-fault isolation beyond the six TMP175 devices currently captured. The Rev C architecture and partial capture are recorded, but schematic completion has **not** reached the approval checkpoint. The layout gate remains closed; no further PCB work is authorized. ## Revision D — Phase 1A schematic capture update — 2026-09-20 ### Completed in the active project - Instantiated schematic-only, datasheet-backed **LM5066IPMH/NOPB** hot-swap control and two **DCM3717S60D13K0TN1** converters without PCB footprints, preserving the Article 10 layout gate. - Implemented a provisional 45 A Class A input chain with fuse placeholders, LTC4359 reverse protection, 0.51 mΩ Kelvin shunt, LM5066I UV/OV/PGD/timer/power-limit support, four-FET pass bank, PMBus, ALERT, remote-temperature input, and a hardware payload-kill node. - Implemented the N+1 48-to-12 V array with individual input fuses, common 12 V output, EAO sharing, EN/FLT control, PMBus, and ceramic input/output bank representations. No liquid-electrolytic capacitor was introduced. - Added a second management CAN channel using STM32 FDCAN1 PD0/PD1, seven additional TMP175 telemetry locations on TCA9548A channels 6/7, and a redundant LMV331/TLV431 analog cold-admission channel. - Captured authoritative COM-HPC power, ground, standby, PWRBTN#, RSTBTN#, SUS_S3#, PLTRST#, SMBus, and connector-J2 PCIe Group 1 x16 plus REFCLK/CLKREQ stubs. All unresolved host-to-OAM mappings use the literal `ENVELOPE-PENDING-SELECTION` token. - Corrected the earlier analog placeholder net to `ANALOG_TEMP_INPUT_ENVELOPE-PENDING-SELECTION`. ### Datasheet-backed provisional values | Item | Revision D capture value | Status | |---|---:|---| | LM5066I shunt | 0.51 mΩ | Provisional cold-rated Kelvin MPN required | | Current limit | 45.88 A minimum, 50.98 A typical | Derived from LM5066I threshold range | | UV/OV divider | 102 kΩ / 1.87 kΩ / 4.53 kΩ | Nominal UV release 44.05 V, UV trip 42.01 V, OV trip 58.87 V, OV release 56.69 V | | PWR resistor | 28.7 kΩ | Approximately 478 W provisional FET power limit | | DCM output ceramic representation | 176 µF nominal per module | Includes 2× nominal allowance pending exact bias/temperature curves | ### Remaining blockers and warnings 1. The authoritative `OAI-OAM_Pinlist_Pinmap_r2.0_v1.0.xlsx` was not available. Exact OAM 48 V, grounds, presence, management, power-brake, reset, power-good, and PCIe ball assignments were therefore **not invented**; provisional J2 remains unmapped. 2. The exact blind-mate entry connector and fuse MPNs remain open. F14/F15/F18 are schematic-only placeholders pending prospective fault current, interrupt rating, time-current, voltage, and cold-temperature evidence. 3. DCM ADDR programming resistors, exact +5 °C trip/+7 °C release analog sensor networks, dry-gas/leak/condensation/flow/pressure/plate-presence inputs, and a separate watchdog transistor kill path remain incomplete. 4. The 5.0SMDJ60A coordination conflict with the OAM 59.5 V ceiling remains unresolved. 5. Current ERC review reports **1,268 open electrical checks**, dominated by intentionally unmapped unused pins on J1/J12 and single-pin named interface stubs. These are release blockers, not approval evidence. 6. The existing default PCB state remains an Article 10 conflict. No PCB placement, board, stackup, footprint, copper, or routing operation was performed during Revision D work. ### Approval state Revision D records substantial Phase 1A architecture capture but does **not** approve the schematic for layout. Required next gates are authoritative OAM mapping, exact protection/entry selections, intentional no-connect treatment of out-of-scope connector pins, ERC cleanup, independent review, and explicit Founder architecture approval before any PCB work. ## Revision D remediation pass — independent-review response — 2026-09-20 ### Safe schematic and documentation corrections completed - Renamed every still-unselected module, backplane, entry, management, analog-sensor, and PCIe interface net to include the exact literal `ENVELOPE-PENDING-SELECTION`. Obsolete controller-pending labels were resolved to `LM5066_GATE_DRIVE` and `LM5066_REMOTE_FET_TEMP`; the authoritative COM-HPC `VIN_PWROK` mapping at J1:C6 is now a resolved staged-release net. - Captured every ICD section 5 enclosure permissive as an explicit MCU input stub without assigning unknown connector pins: dry-gas permissive, leak alarm, condensation alarm, coolant flow, coolant pressure, both cold-plate presence inputs, COM-HPC and OAM module presence, and sensor plausibility. - Made the staged sequence auditable in the schematic: `PAYLOAD_HARD_KILL_N` controls LM5066I UVLO/EN as stage 1; `DCM_ARRAY_ENABLE` releases the 48-to-12 V array as stage 2; `COMHPC_VIN_PWROK` releases the CPU module; OAM enable, power-brake, reset, power-good, and presence remain named `ENVELOPE-PENDING-SELECTION` stubs until the exact OAM ball map is supplied. - Preserved firmware independence of the safety path: both LMV331 comparator outputs and the firmware kill transistor can pull `PAYLOAD_HARD_KILL_N` low. A separate `BACKPLANE_HARD_KILL_OPEN_DRAIN_ENVELOPE-PENDING-SELECTION` interface requirement and MCU monitor stub are recorded; its physical connection to the kill node remains blocked by entry-connector mapping. - Completed the two-channel threshold representation as `+5 C trip / +7 C release / 2 C hysteresis` on both independent analog channels. Exact sensor transfer networks remain explicitly selection-pending rather than guessed. - Resolved DCM array guidance from the authoritative Vicor extract: EN, FLT, SDA, SCL, EAO and common output are interconnected; each input remains individually fused; U19 ADDR is tied directly to ground for address 0x51; U20 is specified as address 0x52 requiring 12.1 kΩ 1% to ground; SYNCI and IMON are no-connect on both modules. The physical 12.1 kΩ component was not added because doing so would create another footprint while Article 10 is closed. - Remediated the Article 7 map without adding footprints: U13 is now the CPU pedestal-edge sensor, U9 and U12 are the OAM and COM-HPC module power-entry sensors, and the existing converter, coolant, plate-edge, leading-edge, backplane-region, and board-center locations remain. Accelerator pedestal-edge SDA/SCL stubs were added with `ENVELOPE-PENDING-SELECTION`; a physical sensor awaits approved mechanical placement. - Applied no-connect status only where the authoritative conga-HPC/sILH Tables 21 and 22 explicitly footnote a pin as **Not connected**, plus the DCM datasheet's explicit factory-use-only terminals. This cleared 120 connector floating-pin errors. Reserved, unsupported, optional, and unmapped pins were deliberately left unresolved. ### Fresh verification evidence - Schematic readback: **97 components, 163 nets** after removal of obsolete empty nets. No component was added. - PCB readback: the pre-existing unauthorized layout still contains **97 elements and 97 footprints** on a default **160 mm × 100 mm, 4-layer** board. This remains a direct ICD Article 10 violation. This remediation performed no board, stackup, placement, footprint, copper, via, fill, or routing mutation and did not increase the footprint count. - Fresh electrical review: **1,162 open ERC findings** — **1,071 floating pins**, **90 single-pin nets**, and **1 warning** for the provisional D1 TVS symbol's unspecified pin types. The prior fresh count was 1,269, so this pass reduced the open ERC population by **107** while adding the required auditable interface stubs. ### Remaining justified blockers 1. Exact OAM r2.0 ball assignments remain unavailable because `OAI-OAM_Pinlist_Pinmap_r2.0_v1.0.xlsx` is missing. J2 is still a provisional non-OAM connector, so OAM power, return, management, kill, presence, power-brake, reset, power-good, and PCIe pins cannot be connected or classified no-connect. 2. The blind-mate 48 V entry connector, protective-earth/return/presence contacts, and exact fuse devices remain unselected. `48V_BUS_RAW_ENVELOPE-PENDING-SELECTION` and the direct external hardware-kill termination therefore remain single-pin or zero-pin requirements. 3. Most of the 1,071 floating-pin findings are COM-HPC/OAM connector pins that are reserved, optional, unsupported, or not used by the carrier but are not explicitly documented as **Not connected** by the authoritative tables. They were not suppressed. 4. The 90 single-pin nets are predominantly named interface stubs that intentionally stop at the module or backplane selection boundary. They remain release blockers until the exact connectors and mappings exist. 5. U20 still requires the resolved 12.1 kΩ 1% address resistor, and the accelerator pedestal location still requires a physical sensor. Adding either now would worsen the unauthorized footprint-placement state; both are held as schematic requirements pending Article 10 remediation and approval. 6. The exact analog temperature sensor/transfer-network implementation that produces the +5 C trip and +7 C release thresholds is still missing. Threshold intent and two independent kill channels are captured, but component values cannot be selected without the sensor transfer function and cold-accuracy budget. 7. The D1 5.0SMDJ60A symbol warning and the larger 59.5 V OAM coordination conflict remain unresolved. D1 is not approved for release. ### Checkpoint state The independent checkpoint is **not reached**. The remediation exhausted safe schematic/document changes that do not require the missing OAM map, entry selection, exact analog sensor transfer data, or modification of the prohibited PCB state. Layout remains blocked by ICD Article 10 and requires an explicit revert/removal strategy plus Founder architecture approval before any physical work.