RS-485 Interface with LDO Design

flux

Based on the Flux knowledge base guidance for serial interfaces and battery-powered LDOs, here’s how to proceed:
  1. RS-485 Interface for LoRa-E5 Module
    • Choose an RS-485 transceiver (e.g., MAX3485, SN65HVD1784).
    • Match logic-level: the module’s UART TX/RX operate at 3.3 V; pick a transceiver with 3.3 V logic-IO support.
    • Add fail-safe bias resistors (typically 680 Ω pull-ups/pull-downs) on A/B lines.
    • Include a 120 Ω termination resistor across A/B if used at cable ends.
    • Place decoupling capacitor (0.1 µF) close to the transceiver’s VCC pin.
  2. Li-Ion Battery with 3.3 V LDO
    • The battery varies from 4.2 V to ~3.0 V when discharged. Based on Flux knowledge base, ensure the LDO dropout voltage is lower than (3.3 V − 3.0 V) = 0.3 V at your max load.
    • Select an LDO with dropout ≤ 0.3 V and low quiescent current (e.g., < 1 µA) to maximize run-time.
    • Add an input bulk capacitor (e.g., 4.7 µF) and an output decoupling capacitor (e.g., 1 µF) per the LDO datasheet.
Next steps:
  • Would you like me to suggest specific Flux-library parts for the RS-485 transceiver and LDO?
  • Or shall I draft the schematic additions (transceiver, resistors, capacitors) for you to review?
A

acefrost

Yes, @library find a 3.3 V RS-485 transceiver with fail-safe bias in an SOIC-8 footprint.

flux

Here are the top match from the Flux library search for a 3.3 V RS-485 transceiver with integrated fail-safe bias in an SOIC-8 footprint:

Table

Part NameMPNManufacturerDescriptionPackageDatasheet
THVD1451DTHVD1451DTexas InstrumentsRS-485 transceiver, 3.3 V to 5 V; 18 kV IEC ESD; integrated fail-safe biasSOIC-8 (3.9×4.9 mm, 1.27 mm pitch)PDF
Recommended: THVD1451D meets the 3.3 V logic, includes fail-safe biasing, and is in a standard SOIC-8 package.
Next steps: would you like to add this transceiver to your schematic and place the associated bias and termination resistors?
Add transceiver and terminators
Ask bias and termination values
Placement advice
Control pin wiring
Calculate bias current
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Files

Pins

Symbol

Layout

3D View

PB15
PC0
PB6
PB3
PB10
PB13
RST
GND
PB7
PB5
PA0
PB0
PB4
PA14
GND
GND
PC1
PA9
PA3
RFIO
PA2
PB14
PA15
PB9
PA10
PA13
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Bus Group
VCC
1
Unspecified
PWR
Left
1
GND
2
Unspecified
GND
Right
6
PA13
3
Unspecified
DEBUG
Left
2
PA14
4
Unspecified
DEBUG
Left
2
PB15
5
Unspecified
IO
I2C2
Left
4
I2C2
PA15
6
Unspecified
IO
Left
4
I2C2
PB4
7
Unspecified
IO
Left
4
PB3
8
Unspecified
IO
Left
4
PB7
9
Unspecified
IO
UART1
Left
4
UART1
PB6
10
Unspecified
IO
UART1
Left
4
UART1
PB5
11
Unspecified
IO
Left
4
PC1
12
Unspecified
IO
LPUART1
Right
4
LPUART1
PC0
13
Unspecified
IO
LPUART1
Right
4
LPUART1
GND
14
Unspecified
GND
Left
6
RFIO
15
Unspecified
RFIO
Right
5
GND
16
Unspecified
GND
Left
6
RST
17
Unspecified
RST
Right
3
PA3
18
Unspecified
IO
USART2
Left
4
USART2
PA2
19
Unspecified
IO
USART2
Left
4
USART2
PB10
20
Unspecified
IO
Right
4
PA9
21
Unspecified
IO
Right
4
GND
22
Unspecified
GND
Right
6
PA0
23
Unspecified
IO
Right
4

Wio-E5 (STM32WLE5JC)