IC2 VREF Warning


The "Component Overrides" review flagged a warning on IC2:VREF.
Reports components that have been modified using the "!important" flag.
Designator: IC2:VREF; Ruleset: IC2 VREF pad6 correction
Context: This check flags items that have been modified using the "!important" flag.
Help me fix this.
I confirmed the warning comes from the IC2 VREF pad6 correction ruleset, which forces VREF’s position to X = 1.25 mm, Y = 0.95 mm using !important; it does not itself indicate an electrical error.
In Agent mode, I’ll try removing only the !important flags, verify that VREF stays at the corrected position, and recheck the warning—rather than deleting the pad correction blindly.
Continue in Agent Mode

Firmware Getting Started
Final follow-up hardware status — 2026-10-06
U13 OE is no longer permanentlyLOW: Q1/R1/R2/R3 provides fully-off receiver disconnect, not a guaranteed CH340-valid powergood threshold; do not rely on firmware to fix analog ramp/brownout backfeed. U4 sourceverified mapping now wired; DAC operation remains bench-unvalidated and machine tests prohibited. GPIO map unchanged. No build/flash/USB enumeration tests performed.109components/112nets,ERC14Errors/0Warnings; release blockers/evidence in connection-implementation-review supersede previous counts and open-U4 statements.
Authoritative MCU/programming revision — 2026-10-06
The open-supply/export-continuity and inherited-UART statements below are SUPERSEDED historical baseline. Flat U14 ESP32-WROOM-32U directly implements the SAME fourteen GPIO assignments in the table; schematic memberships verified after U1 removal. GPIO36 is SENSOR_VP and39 SENSOR_VN. UART0 GPIO3/RXD0 connects U15 TXD2; GPIO1/TXD0 connects U15 RXD3. EN/GPIO0 controlled by audited Q3/Q4 cross-coupled SS8050 circuit,10k pulls/base resistors and1uF EN RC. No S1 mode switch exists.
Use separate J3 for programming and J2 only for charging. U14/U15 need approved receiver MAIN_3V3 power; J3 VBUS powers only U16/U13 logic and cannot intentionally power receiver. Power-off USB data injection remains a HARDWARE release blocker because U13 OE is tied LOW; resolve it before treating USB-only plugging as safe. No compilation, flash, USB enumeration or automatic-download test performed. Toolchain/dependency versions and flash size still need review for exact32U variant.
Bench initialization fragment below remains documentation only; no production command/default/link-loss behavior chosen. U4 has no operational isolated supply. Never run diagnostic DAC sweeps on a machine; retain isolated dummy-load and operator-authorization restrictions. This change verifies schematic GPIO continuity, not physical board operation or firmware safety.
Historical starter context (GPIO table still current)
Status: documentation-only starter, not compiled, flashed or validated. Current host wiring is real; U1 export-to-internal MCU continuity is UNVERIFIED and supplies remain deliberately open. Do not interpret this pin table as confirmed electrical continuity.
Current host GPIO map

Table


ExportHost netIntended peripheral
GPIO18RADIO_SCKSPI clock
GPIO19RADIO_MISOSPI input
GPIO23RADIO_MOSISPI output
GPIO27RADIO_NSSRadio chip select
GPIO14RADIO_BUSYRadio busy input
GPIO13RADIO_DIO1Radio interrupt input
GPIO4RADIO_NRSTRadio reset
GPIO16RADIO_RXENRF receive enable
GPIO17RADIO_TXENRF transmit enable
GPIO21SDA_MAINI2C SDA to U2
GPIO22SCL_MAINI2C SCL to U2
GPIO34BAT_ADCBattery analog input
GPIO36CHARGER_PGCharger power-good input
GPIO39CHARGER_STATCharger status input
GPIO34/36/39 are intended input-only uses; status pull-ups are host resistors. No user PWM/timer output is assigned. Original TX/RX UART and boot/reset inherited module circuit are unresolved integration items. Do not reassign flash-related SD*/CLK/CMD exports.
Toolchain and dependencies
A provisional Arduino-ESP32 diagnostic project is a familiar starting point; exact framework version, module target and flash settings must be pinned after module repair. Dependencies: Arduino-ESP32 SPI and Wire plus an audited SX1262/E22 driver. A generic SX1262 library may require explicit RXEN/TXEN control rather than automatic DIO2 switching (host DIO2 is NC). DAC driver must specifically implement MCP4726 commands, reference/gain and EEPROM semantics, not assume MCP4725 compatibility. No dependency lock or executable is delivered here.
Example CLI workflow after installing Arduino CLI and reviewing board target: arduino-cli core install esp32:esp32; arduino-cli compile --fqbn . Upload only after boot/USB-UART and module continuity review. Build/flash remain UNATTEMPTED.
Peripheral initialization sketch fragment

Cpp


#include <SPI.h>
#include <Wire.h>
constexpr int SCK_PIN=18, MISO_PIN=19, MOSI_PIN=23, NSS_PIN=27;
constexpr int BUSY_PIN=14, DIO1_PIN=13, RESET_PIN=4;
constexpr int RXEN_PIN=16, TXEN_PIN=17;
constexpr int SDA_PIN=21, SCL_PIN=22;
constexpr int BAT_PIN=34, PG_PIN=36, STAT_PIN=39;
void initBenchInterfaces() {
  // Dummy-load bench only; does NOT define welding command policy.
  pinMode(NSS_PIN, OUTPUT); digitalWrite(NSS_PIN, HIGH);
  pinMode(RXEN_PIN, OUTPUT); digitalWrite(RXEN_PIN, LOW);
  pinMode(TXEN_PIN, OUTPUT); digitalWrite(TXEN_PIN, LOW);
  pinMode(BUSY_PIN, INPUT); pinMode(DIO1_PIN, INPUT);
  pinMode(PG_PIN, INPUT); pinMode(STAT_PIN, INPUT);
  pinMode(BAT_PIN, INPUT);
  SPI.begin(SCK_PIN, MISO_PIN, MOSI_PIN, NSS_PIN);
  Wire.begin(SDA_PIN, SCL_PIN); Wire.setClock(100000);
  // RESET sequence and interrupts require reviewed E22 driver timings.
  // No DAC command, EEPROM write or machine actuation here.
}
int readBatteryRaw() { return analogRead(BAT_PIN); }
int readPgRaw() { return digitalRead(PG_PIN); }
int readStatRaw() { return digitalRead(STAT_PIN); }
This fragment is not a complete application. SDK handles crystal/PLL defaults; no custom clock config justified. Disable unused Wi-Fi/Bluetooth only through reviewed SDK configuration, and quantify current before making power claims. Serial console initialization awaits inherited UART/USB audit. ADC attenuation/calibration and divider transfer must be reviewed before converting raw readings into voltage. Never enable both TXEN and RXEN simultaneously; driver transitions must be tested with scope.
Startup and operating sequence
  1. Validate rails and continuity; keep machine physically disconnected.
  2. Initialize bench GPIO and bus clocks; confirm charger-status inputs and calibrated battery measurement.
  3. Initialize radio using reviewed E22 timings, BUSY handshake and legal region settings. Validate transport on dummy setup before application command handling.
  4. Probe approved DAC address and read status/configuration including EEPROM power-up behavior. Do not automatically write a presumed safe analog value.
  5. Gate any diagnostic DAC sweep behind explicit operator authorization and isolated dummy load. Calculate output code only after reference/gain/load calibration.
  6. Application startup/link-loss/brownout/watchdog/stale-command behavior remains USER DECISION. No placeholder zero/hold/full-scale policy may be shipped; reject production enable until policy and tests exist.
Firmware requirements backlog
Pairing/authentication, packet versioning/CRC, sequence/replay protection, freshness timeout, bounded command range, explicit state machine, watchdog, transport diagnostics, calibration storage, battery reporting and audit logs. Timer frequencies/timeouts, machine semantics and RF settings are deliberately unspecified pending requirements. Test reset/link-loss and retained DAC EEPROM output independently; firmware cannot alone guarantee output de-energization without reviewing hardware behavior.
  • Final follow-up hardware status — 2026-10-06

  • Authoritative MCU/programming revision — 2026-10-06

  • Historical starter context (GPIO table still current)

  • Current host GPIO map

  • Toolchain and dependencies

  • Peripheral initialization sketch fragment

  • Startup and operating sequence

  • Firmware requirements backlog