Routing is now down to three missing connections: R6–R5 ground and the two USB data lines between D1 and U5; fresh checks report no copper-overlap errors, but this is not yet an order-ready board. Their escape paths are blocked by existing copper; USB verification and manufacturing-export checks still remain, so I cannot give a defensible release time.
I’ll repair only the three blocked connections, preserving unaffected routing and your fixed board constraints. Then I’ll check connectivity and USB geometry before generating and verifying the manufacturing package.
I started the authorized local repair, but couldn’t retrieve and verify its final results before execution stopped. I cannot confirm that the three remaining connections are fixed.
The last verified state has three airwires: the R6–R5 ground connection and both USB data connections between D1 and U5. No copper-overlap errors were reported in the last checks; charging remains inhibited.
Next is to recover the saved repair results, verify connectivity and USB geometry, then resolve assembly-export exclusions and check the manufacturing package. No verified production package was delivered this session.
Power the switched 3.3 V rail and connect an external standards-compatible SWD probe to the five compact probe pads: VTref, GND, SWDIO, SWDCLK, RESET. J3 is only the schematic mapping and is excluded from the physical BOM/PCB.
Flash and verify an nRF52833-compatible USB bootloader build adapted for this exact board pin map.
Confirm reset, USB enumeration, application handoff, and recovery before relying on USB updates.
A practical software starting point is an open-source nRF52 USB DFU bootloader such as the Adafruit nRF52 bootloader, but DWM3001C/nRF52833 board support, flash layout, USB identifiers, reset behavior, and any boot button policy must be ported and tested. No compiled bootloader or proven programming flow is included in this revision. Avoid assuming any proprietary probe license; use any compatible SWD probe/toolchain supported by the selected workflow.
Bootloader Entry
SW2 provides reset access. A compatible double-reset bootloader can use this for entry after it has first been installed over SWD. There is no guessed GPIO boot button in the schematic.
Critical Verification
Bench-check whether micro-USB VBUS at U1 VUSB can source or back-power internal/module rails when 3V3_SW is off. Until measured, do not claim the module is electrically dark with a native USB cable attached.
Authoritative nRF52833 VBUS-with-VDD-off evidence was still indexing during this revision. No VUSB isolation switch was guessed or added. Native USB update behavior therefore remains a bench and evidence gate; the bootloader is still instructions only, not compiled or tested firmware.
USB_DP and USB_DN now carry schematic differential-pair/controlled-impedance metadata for later 90 Ω differential routing. No bootloader binary has been compiled, installed, or tested.