I’m proceeding without the independent topology review because that service failed; I’ll still validate the schematic after wiring.I’ll continue with the built-in checks and keep the analog current loop conservative: low setpoint voltage, gate clamp, and hardware scaling to limit current.Part sourcing is the next step; I’ll use real library components for ICs/connectors/semiconductors and generic passives for resistors/caps/inductors.I’m looking up the exact available schematic/library tools now so I can add parts cleanly instead of guessing part identifiers.I’m going to add the main ICs and support parts in functional blocks once the library part IDs are confirmed; if a preferred part isn’t present, I’ll use a close documented alternative.I can’t continue editing the project right now because the account has no available ACUs, so AI project-editing features are unavailable.
What’s established:
Corrected direction: this should be a programmable negative current source in system terms.
Target architecture: +24 V input → inverting DC/DC rail around -24 V → PMOS/op-amp controlled negative current output → 0–100 mA hardware-scaled control → 16-bit ADC readback → minimal ESP32 anchor.
No schematic components or nets have been added yet.
Remaining work once ACUs are available:
Select actual library parts.
Add and wire the inverting converter, current-source loop, DAC, ADC, ESP32/module anchor, connectors, and passives.
Draft design for an ESP32-controlled programmable negative-voltage constant-current supply. The board accepts +24 V input, generates an inverted negative rail, uses an LT3094 as the low-noise negative output/current-regulation element, and provides ESP32 digital control plus 16-bit ADC readback of output voltage and current.
Intended Use
Prototype/validation PCB for a programmable negative current source/supply controlled over firmware. Intended for bench or embedded use where output current is limited to 100 mA maximum.
What the Device Should Do
Accept a positive 24 V DC input.
Invert the input to create a negative supply rail for the LT3094.
Provide a programmable negative output using an ESP32-controlled digital potentiometer.
Limit maximum output current to 100 mA.
Read back output voltage and output current using external 16-bit ADCs, not ESP32 internal ADCs.
Main Features
ESP32 module control and I2C/SPI peripheral bus.
Inverting DC/DC converter from +24 V to a negative rail.
LT3094 negative linear regulator/current source stage.
Digitally programmable current/voltage set network.
External 16-bit ADC readback for voltage and current telemetry.
Input/output connectors and test points for bring-up.
System Architecture
Diagram
Hardware Subsystems
Power input: +24 V DC connector with protection and bulk capacitance.
Negative rail generation: inverting switch-mode converter sized above 100 mA output plus LT3094 headroom.
Output stage: LT3094 configured as programmable negative supply/current-limited source.
MCU/control: ESP32 module powered from local 3.3 V rail.
Readback: external 16-bit ADC(s) for scaled output voltage and current sense measurement.
Interfaces and Connections
+24 V input connector.
Negative output connector.
ESP32 programming/debug interface.
I2C or SPI for digital potentiometer and 16-bit ADC.
Test points for +24 V, 3V3, negative raw rail, output, current sense, SDA/SCL/SPI.
Power and Runtime Expectations
Externally powered from +24 V DC. No battery/runtime target specified.
Power Tree and Power Budget
Initial sizing assumptions: output current maximum 100 mA; ESP32 3.3 V rail peak allowance approximately 500 mA; negative converter sized with margin for LT3094 headroom and losses. Detailed power budget will be recorded in Design Notes.
Manufacturing and Assembly Expectations
Default to SMD professional PCB assembly unless the user requests hand-solderable parts.
Firmware-Relevant Hardware Requirements
Firmware must initialize the ESP32, configure the digital potentiometer, read the external 16-bit ADC(s), compute scaled output voltage/current, and enforce software current limits in addition to hardware limiting.
Physical Design Expectations
Board size and enclosure are not yet specified. Layout should separate noisy inverting converter currents from LT3094/ADC analog sensing and keep ESP32 antenna at board edge.
Important Design Decisions
Use an external 16-bit ADC for all analog readback.
Use LT3094 for negative post-regulation/current-control stage.
Use an ESP32 module rather than bare ESP32 silicon.
Use a switching inverter before the LT3094 because the input is +24 V and the output must be negative.
Assumptions
SMD assembly is acceptable.
Output negative voltage range is not specified; initial design will choose a conservative negative raw rail compatible with 100 mA operation and LT3094 headroom.
Communication to ADC and digital potentiometer will use I2C unless selected parts require SPI.
Change Notes
Initial specification created from user request on 2026-07-15.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes
Reviews
Documents
Project Specification
Assets
Assets are files uploaded to this project which can be used in various ways.
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