I’m proceeding without the independent topology review because that service failed; I’ll still validate the schematic after wiring.I’ll continue with the built-in checks and keep the analog current loop conservative: low setpoint voltage, gate clamp, and hardware scaling to limit current.Part sourcing is the next step; I’ll use real library components for ICs/connectors/semiconductors and generic passives for resistors/caps/inductors.I’m looking up the exact available schematic/library tools now so I can add parts cleanly instead of guessing part identifiers.I’m going to add the main ICs and support parts in functional blocks once the library part IDs are confirmed; if a preferred part isn’t present, I’ll use a close documented alternative.I can’t continue editing the project right now because the account has no available ACUs, so AI project-editing features are unavailable.
What’s established:
- Corrected direction: this should be a programmable negative current source in system terms.
- Target architecture: +24 V input → inverting DC/DC rail around -24 V → PMOS/op-amp controlled negative current output → 0–100 mA hardware-scaled control → 16-bit ADC readback → minimal ESP32 anchor.
- No schematic components or nets have been added yet.
Remaining work once ACUs are available:
- Select actual library parts.
- Add and wire the inverting converter, current-source loop, DAC, ADC, ESP32/module anchor, connectors, and passives.
- Run ERC/design review and fix any issues.