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Functional Verification Report

Review date: 2026-09-01
Scope: Read-only review of the current schematic and PCB. No fixes were applied.
Evidence policy: PASS means confirmed from live project data and, where required, immutable datasheet evidence. FAIL means live project data demonstrates a functional or manufacturing defect. UNVERIFIED means the required external evidence or physical mapping was unavailable. Datasheet indexing returned “immutable evidence not ready” for the TPIC6B595 and SN74AHCT125 queries, so claims requiring datasheet clauses are not promoted to PASS.

Executive result

Overall: FAIL. The schematic signal topology is coherent, but the board has active PCB errors and the 12 V-to-5 V linear-regulator architecture has a severe thermal ri...

flux

Completed the read-only functional review in Functional Verification Report.

Overall: FAIL. Primary blockers are J1/J3/DS1 placement and copper conflicts, LM1117 thermal dissipation, unsafe/unverified USB–12 V power interaction, and the unverified 40101B-5 pinout. No design changes were applied.

brianbenchoff

tell me what this board is supposed to do and how you accomplished it, new document in the files

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Created a project doc

Purpose and Implementation

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Purpose and Implementation What This Board Is Supposed to Do

The Days Since Counter is a large, network-capable two-digit counter intended to show the number of days since a selected event. Typical uses include “days since the last incident,” “days since a milestone,” or any other value that can be represented from 00 to 99.

The Raspberry Pi Pico 2 W provides the intelligence and wireless connectivity. Firmware determines the value to display—either by calculating elapsed days from a stored date or by receiving an updated value over Wi-Fi—and converts the two decimal digits into seven-segment patterns.

The board is designed as a self-contained sign:

A 12 V DC input powers the board.
Two large common-anode seven-segment modules provide the visible digits.

flux

Created Purpose and Implementation. It explains the board’s intended “days since” function, power architecture, Pico firmware role, logic buffering, serial display drivers, LED current paths, expansion bus, and physical PCB implementation.

Files

Schematic

Layout

3D View

Board Parts and Connections

Scope

This file documents the live schematic for the Days Since Counter. It covers all 38 component instances and all 46 named nets present when generated. Connections are logical schematic connections; PCB routing status is outside this file's scope.

System Overview

The board accepts +12 V through J1, powers two large common-anode seven-segment displays directly from +12 V, and produces +5 V with U4 for the Raspberry Pi Pico 2 W, logic buffer, and display drivers. U1 emits three control signals through U5. U3 receives serial DATA and cascades into U2; both TPIC6B595 drivers sink the display segment currents through R1-R16. J2 and J3 expose the power and control bus.

Component Inventory

Controller and Logic Interface

Table

Ref	Part	Configuration	Purpose and connections
U1	Raspberry Pi Pico 2 W Shield SMD	Pico 2 W module; VSYS-powered; VBUS intentionally unconnected	Main controller. GPIO19 drives U5.1A, GPIO18 drives U5.2A, GPIO17 drives U5.3A. VSYS is on +5V. All GND and AGND pins are on GND. Other unused GPIO, debug, ADC, 3V3, enable, RUN, test, and VBUS pins are intentionally not used by this circuit.
U5	SN74AHCT125DR	SOIC-14; 5 V quad buffer	Converts the Pico's 3.3 V control outputs to 5 V logic. 1A receives GPIO19 and 1Y feeds R17/DATA. 2A receives GPIO18 and 2Y feeds R18/SRCK. 3A receives GPIO17 and 3Y feeds R19/RCK. All four active-low output enables, 4A, and GND are tied to GND; 4Y is unused. VCC is +5V.
R17	Generic resistor	33 ohm, 1%, 0805	Series damping between U5.1Y and DATA.
R18	Generic resistor	33 ohm, 1%, 0805	Series damping between U5.2Y and SRCK.
R19	Generic resistor	33 ohm, 1%, 0805	Series damping between U5.3Y and RCK.
C5	Generic capacitor	100 nF ceramic, 10 V, 0805	U5 supply decoupling from +5V to GND.

Display Drivers

Table

Ref	Part	Configuration	Purpose and connections
U2	TPIC6B595DWR	TI power shift register, SOIC-20, LCSC C7094	Drives DS1 through R1-R8. VCC pin 2 is +5V; GND pins 10, 11, 19 and /G pin 9 are GND. /SRCLR pin 8 is SRCLR_N, RCK pin 12 is RCK, and SRCK pin 13 is SRCK. SER IN pin 3 receives SER_CASCADE from U3 SER OUT. DRAIN0-7 drive R1-R8 respectively. SER OUT and NC pins 1/20 are unused.
U3	TPIC6B595DWR	TI power shift register, SOIC-20, LCSC C7094	First serial display driver; drives DS2 through R9-R16. VCC pin 2 is +5V; GND pins 10, 11, 19 and /G pin 9 are GND. /SRCLR pin 8 is SRCLR_N, RCK pin 12 is RCK, and SRCK pin 13 is SRCK. SER IN pin 3 receives DATA. SER OUT pin 18 drives U2 SER IN through SER_CASCADE. DRAIN0-7 drive R9-R16 respectively. NC pins 1/20 are unused.
R20	Generic resistor	10 kohm, 1%, 0805	Pulls shared SRCLR_N high to +5V so both TPIC shift registers remain enabled unless actively cleared.
C6	Generic capacitor	100 nF ceramic, 10 V, 0805	U2 supply decoupling from +5V to GND.
C7	Generic capacitor	100 nF ceramic, 10 V, 0805	U3 supply decoupling from +5V to GND.

Displays

Table

Ref	Part	Configuration	Purpose and connections
DS1	40101B-5	Large common-anode seven-segment display; pins 1-10 = CA1, E, D, C, DP, B, A, CA2, F, G	Left display. CA1 and CA2 connect to +12V. Segment pins A-G and DP connect through R1-R8 to U2 DRAIN0-DRAIN7.
DS2	40101B-5	Large common-anode seven-segment display; pins 1-10 = CA1, E, D, C, DP, B, A, CA2, F, G	Right display. CA1 and CA2 connect to +12V. Segment pins A-G and DP connect through R9-R16 to U3 DRAIN0-DRAIN7.

DS1 Segment Resistors

Table

Ref	Value/package	Display side	Driver side
R1	220 ohm, 0805	P1 -> DS1 A	P2 -> U2 DRAIN0
R2	220 ohm, 0805	P1 -> DS1 B	P2 -> U2 DRAIN1
R3	220 ohm, 0805	P1 -> DS1 C	P2 -> U2 DRAIN2
R4	220 ohm, 0805	P1 -> DS1 D	P2 -> U2 DRAIN3
R5	220 ohm, 0805	P1 -> DS1 E	P2 -> U2 DRAIN4
R6	220 ohm, 0805	P1 -> DS1 F	P2 -> U2 DRAIN5
R7	220 ohm, 0805	P1 -> DS1 G	P2 -> U2 DRAIN6
R8	1 kohm, 0805	P1 -> DS1 DP	P2 -> U2 DRAIN7

DS2 Segment Resistors

Table

Ref	Value/package	Display side	Driver side
R9	220 ohm, 0805	P1 -> DS2 A	P2 -> U3 DRAIN0
R10	220 ohm, 0805	P1 -> DS2 B	P2 -> U3 DRAIN1
R11	220 ohm, 0805	P1 -> DS2 C	P2 -> U3 DRAIN2
R12	220 ohm, 0805	P1 -> DS2 D	P2 -> U3 DRAIN3
R13	220 ohm, 0805	P1 -> DS2 E	P2 -> U3 DRAIN4
R14	220 ohm, 0805	P1 -> DS2 F	P2 -> U3 DRAIN5
R15	220 ohm, 0805	P1 -> DS2 G	P2 -> U3 DRAIN6
R16	1 kohm, 0805	P2 -> DS2 DP	P1 -> U3 DRAIN7

Power Input and Regulation

Table

Ref	Part	Configuration	Purpose and connections
J1	Tensility 54-00164	Board-edge DC barrel jack	+12 V input. Pin B is +12V. Pins A1 and A2 are GND. Switched contact C is not used.
U4	LM1117IMPX-5.0/NOPB	Fixed 5 V LDO, SOT-223	Converts +12V to +5V. VI pin 3 is +12V, GND pin 1 is GND, and both VO pins 2 and 4 are +5V.
C1	Generic capacitor	100 nF ceramic, 25 V, 0805	High-frequency input bypass from +12V to GND at U4.
C2	Generic capacitor	10 uF tantalum, 25 V, 1206	U4 input bulk capacitor from +12V to GND.
C3	Generic capacitor	10 uF tantalum, 16 V, 1206; required ESR 0.3-22 ohm	U4 output stability capacitor from +5V to GND.
C4	Generic capacitor	100 uF aluminum electrolytic, 25 V, CP_Elec_8x10	+12V input bulk storage from +12V to GND near J1.

Expansion Headers and Marking

Table

Ref	Part	Purpose and pinout
J2	1x6, 2.54 mm vertical header	Expansion bus: pin 1 +12V, pin 2 GND, pin 3 +5V, pin 4 DATA, pin 5 SRCK, pin 6 RCK.
J3	1x6, 2.54 mm vertical header	Mirrored expansion bus with the same logical pinout as J2: pin 1 +12V, pin 2 GND, pin 3 +5V, pin 4 DATA, pin 5 SRCK, pin 6 RCK.
Flux Logo1	Flux Logo silkscreen	50.8 mm / 2 in "Made with Flux" rear-board marking. Excluded from BOM and pick-and-place; has no electrical pins.

Complete Net and Connection List

Table

Net	Connected pins	Function
+12V	J1:B; U4:VI(3); C1:P1; C2:P1; C4:P1; DS1:CA1(1), CA2(8); DS2:CA1(1), CA2(8); J2:1; J3:1	Raw input and display common-anode supply.
+5V	U4:VO(2), VO(4); C3:P1; U1:VSYS(39); U5:VCC(14); C5:P1; C6:P1; C7:P1; R20:P2; J2:3; J3:3; U2:VCC(2); U3:VCC(2)	Regulated logic supply.
GND	J1:A1,A2; U4:GND(1); C1-C7:P2; U1:GND pins 3,8,13,18,23,28,38,42 and AGND(33); U5:GND(7), /1OE(1), /2OE(4), /3OE(10), /4OE(13), 4A(12); J2:2; J3:2; U2:GND(10,11,19), /G(9); U3:GND(10,11,19), /G(9)	Common return; also permanently enables the used AHCT outputs and TPIC outputs.
GP19_TO_1A	U1:GPIO19(25); U5:1A(2)	Pico serial-data source into buffer channel 1.
GP18_TO_2A	U1:GPIO18(24); U5:2A(5)	Pico shift-clock source into buffer channel 2.
GP17_TO_3A	U1:GPIO17(22); U5:3A(9)	Pico latch-clock source into buffer channel 3.
U5_1Y_SERIES	U5:1Y(3); R17:P1	Buffered DATA before series resistor.
DATA	R17:P2; U3:SER IN(3); J2:4; J3:4	Serial display data and exported bus signal.
U5_2Y_SERIES	U5:2Y(6); R18:P1	Buffered SRCK before series resistor.
SRCK	R18:P2; U2:SRCK(13); U3:SRCK(13); J2:5; J3:5	Shift-register serial clock.
U5_3Y_SERIES	U5:3Y(8); R19:P1	Buffered RCK before series resistor.
RCK	R19:P2; U2:RCK(12); U3:RCK(12); J2:6; J3:6	Shift-register storage/latch clock.
SRCLR_N	R20:P1; U2:/SRCLR(8); U3:/SRCLR(8)	Shared active-low shift-register clear, pulled up to +5V.
SER_CASCADE	U3:SER OUT(18); U2:SER IN(3)	Serial cascade from first driver U3 into second driver U2.
U2_DRAIN0	U2:DRAIN0(4); R1:P2	DS1 A sink path, driver side.
DS1_A	R1:P1; DS1:A(7)	DS1 A segment, display side.
U2_DRAIN1	U2:DRAIN1(5); R2:P2	DS1 B sink path, driver side.
DS1_B	R2:P1; DS1:B(6)	DS1 B segment, display side.
U2_DRAIN2	U2:DRAIN2(6); R3:P2	DS1 C sink path, driver side.
DS1_C	R3:P1; DS1:C(4)	DS1 C segment, display side.
U2_DRAIN3	U2:DRAIN3(7); R4:P2	DS1 D sink path, driver side.
DS1_D	R4:P1; DS1:D(3)	DS1 D segment, display side.
U2_DRAIN4	U2:DRAIN4(14); R5:P2	DS1 E sink path, driver side.
DS1_E	R5:P1; DS1:E(2)	DS1 E segment, display side.
U2_DRAIN5	U2:DRAIN5(15); R6:P2	DS1 F sink path, driver side.
DS1_F	R6:P1; DS1:F(9)	DS1 F segment, display side.
U2_DRAIN6	U2:DRAIN6(16); R7:P2	DS1 G sink path, driver side.
DS1_G	R7:P1; DS1:G(10)	DS1 G segment, display side.
U2_DRAIN7	U2:DRAIN7(17); R8:P2	DS1 decimal-point sink path, driver side.
DS1_DP	R8:P1; DS1:DP(5)	DS1 decimal point, display side.
U3_DRAIN0	U3:DRAIN0(4); R9:P2	DS2 A sink path, driver side.
DS2_A	R9:P1; DS2:A(7)	DS2 A segment, display side.
U3_DRAIN1	U3:DRAIN1(5); R10:P2	DS2 B sink path, driver side.
DS2_B	R10:P1; DS2:B(6)	DS2 B segment, display side.
U3_DRAIN2	U3:DRAIN2(6); R11:P2	DS2 C sink path, driver side.
DS2_C	R11:P1; DS2:C(4)	DS2 C segment, display side.
U3_DRAIN3	U3:DRAIN3(7); R12:P2	DS2 D sink path, driver side.
DS2_D	R12:P1; DS2:D(3)	DS2 D segment, display side.
U3_DRAIN4	U3:DRAIN4(14); R13:P2	DS2 E sink path, driver side.
DS2_E	R13:P1; DS2:E(2)	DS2 E segment, display side.
U3_DRAIN5	U3:DRAIN5(15); R14:P2	DS2 F sink path, driver side.
DS2_F	R14:P1; DS2:F(9)	DS2 F segment, display side.
U3_DRAIN6	U3:DRAIN6(16); R15:P2	DS2 G sink path, driver side.
DS2_G	R15:P1; DS2:G(10)	DS2 G segment, display side.
U3_DRAIN7	U3:DRAIN7(17); R16:P1	DS2 decimal-point sink path, driver side.
DS2_DP	R16:P2; DS2:DP(5)	DS2 decimal point, display side.

Intentionally Unused Pins

U1: VBUS is intentionally unconnected because the design is powered through VSYS. Unused GPIO, ADC, debug, RUN, 3V3, 3V3_EN, ADC_VREF, SWD, and test-point terminals are not part of the counter interface.
U2: NC pins 1 and 20 and SER OUT pin 18 are unused.
U3: NC pins 1 and 20 are unused; SER OUT is used for the cascade.
U5: 4Y is unused; channel 4 input and enable are grounded.
J1: switched contact C is unused.
Flux Logo1: no electrical terminals.

Signal Flow Summary

J1 supplies +12V.
U4 regulates +12V to +5V for U1, U5, U2, and U3.
U1 GPIO19/18/17 generate DATA/SRCK/RCK through U5 and R17/R18/R19.
U3 receives DATA, drives DS2, and passes shifted serial data through SER_CASCADE to U2.
U2 drives DS1.
Each TPIC output sinks current through its assigned segment resistor; both display common-anode pins remain on +12V.
J2 and J3 expose +12V, GND, +5V, DATA, SRCK, and RCK.

Scope
System Overview
Component Inventory
Controller and Logic Interface
Display Drivers
Displays
DS1 Segment Resistors
DS2 Segment Resistors
Power Input and Regulation
Expansion Headers and Marking
Complete Net and Connection List
Intentionally Unused Pins
Signal Flow Summary