BoothBoss Controller v1.0 is a production-intent controller PCB for a 360 photo booth. It integrates the ESP32 controller, USB programming, dual-BTS7960 motor bridge, HX711 load-cell interface, protected 12 V input, regulated 5 V/3.3 V rails, and three addressable-LED interfaces.
Intended Use
Indoor commercial photo-booth controller powered from an external 12 V supply. The board drives a 12 V gearmotor, reads a four-wire load cell and arm-position sensor, provides USB programming/debug, and drives three addressable-LED data outputs.
What the Device Should Do
Program/debug an ESP32-WROOM-32E through USB-C and CP2102N.
Drive a 12 V DC motor at 20 kHz using a dual-BTS7960B full bridge.
Measure motor current on GPIO35.
Read a four-wire load cell through HX711 Channel A at gain 128 and 10 SPS.
Read an external 3.3 V arm sensor.
Drive three LED data outputs through a 5 V 74AHCT125.
Monitor protected 12 V on GPIO34.
Expose reserved GPIOs only through the expansion header.
Main Features
ESP32-WROOM-32E-N4 with antenna keepout/edge-placement intent.
USB-C USB 2.0 data-only interface and CP2102N-A02-GQFN24.
Manual EN/BOOT and cross-coupled DTR/RTS auto-programming.
Two BTS7960B half bridges in IBT-2-equivalent full-bridge topology.
MP2315SGJ-Z 5 V/3 A buck and AMS1117-3.3 3.3 V regulator.
HX711 with S8550 regulated ~4.3 V analog/excitation rail.
Two externally powered LED data connectors and one board-powered fused LED connector.
System Architecture
Diagram
Hardware Subsystems
MCU and Programming
ESP32-WROOM-32E-N4. EN uses 10 kΩ/1 µF, GPIO0 uses a 10 kΩ pull-up, and both have manual buttons. CP2102N DTR/RTS drive the standard two-NPN cross-coupled auto-program network. UART0 is shared with the debug header.
USB
USB4215-03-A receptacle with independent 5.1 kΩ CC1/CC2 pull-downs and USBLC6-2SC6 data-line ESD protection. USB_VBUS is isolated by net name from board 5V and is used only through the CP2102N self-powered VBUS-sense divider. The board is not powered from USB.
Input and Power
J1: Phoenix Contact 1729128, 2-position 5.08 mm, 17.5 A.
F1: PCB ATO holder populated with a 15 A blade fuse.
SMBJ15A-13-F across fused 12 V and GND.
Motor branch is direct 12V_MOTOR.
Logic branch uses AO4407A-compatible P-MOSF reverse protection with 10 kΩ gate pull-down and 12 V VGS clamp.
MP2315SGJ-Z uses its 5 V reference circuit: 4.7 µH/6 A inductor, bootstrap network, 22 µF input ceramic, 66 µF nominal output ceramics, and reference feedback/AAM/EN values.
MP2315S has no PGOOD pin; normal 5 V and 3.3 V rail LEDs are used.
Two BTS7960B devices drive J2 (M+, M-). Each has 470 nF plus 100 nF local motor-rail ceramics and a 5.1 kΩ slew-rate resistor. Motor bulk is Panasonic EEU-FR1E222L, 2200 µF/25 V. Control inputs include 10 kΩ series protection resistors.
HX711
HX711 DVDD is 3.3 V. VSUP and S8550 emitter use 5 V; the on-chip regulator drives the PNP base. A 20 kΩ/8.2 kΩ divider targets about 4.3 V AVDD. RATE and XI are low, Channel B and XO are unused, and Channel A has 100 Ω series resistors plus a 10 nF differential filter.
LED Outputs
SN74AHCT125DR runs from 5 V. Three channels have OE low and translate GPIO5/18/19. Each connector output has 330 Ω series resistance. The fourth channel is disabled with OE high, input low, and output no-connect.
External 12 V source. Motor is limited by the application to ≤8 A continuous and ≤20 A stall. The board-powered LED3 load is approximately 1.5 A. Logic plus LED3 produces an estimated 5 V worst case near 2.5 A.
Power Tree and Power Budget
Table
Rail
Worst-case load
Design rating / note
12V_MOTOR
8 A continuous, 20 A stall
15 A ATO fuse; stall duration must be short enough for fuse time-current curve
5V
~2.5 A
MP2315S rated 3 A; input from 12 V is roughly 1.16 A at 90% efficiency
3V3
~0.5–0.7 A peak
AMS1117 rated 1 A, but thermal dissipation is ~0.85–1.19 W at this range
HX_AVDD_E+
~1.5 mA plus load-cell bridge
~4.3 V from HX711/S8550 regulator
Manufacturing and Assembly Expectations
100 mm × 80 mm board in PCB phase.
M3 NPTH positions: (5,5), (95,5), (5,75), (95,75) mm.
Terminals, headers, fuse holder, and bulk electrolytics may be hand-soldered on the same side.
Prefer JLCPCB/LCSC stockable parts; extended parts are acceptable where necessary.
12 V high-current copper must be sized for 15 A.
Firmware-Relevant Hardware Requirements
20 kHz motor PWM on GPIO25/26.
GPIO35 and GPIO34 are input-only ADC pins.
HX711 defaults to Channel A/gain 128 after reset; firmware must issue 25 SCK pulses per reading to retain this mode.
GPIO15 is a strapping pin and has no on-board pulldown.
GPIO23 is test-point only.
Physical Design Expectations
ESP32 antenna at a board edge with no copper/components under the antenna keepout.
Keep high-current motor loop away from HX711 analog inputs.
Use one electrical GND net, with quiet/Kelvin routing for HX711 and BTS7960 sense returns.
Place decoupling at the relevant pins and route USB D+/D- as a 90 Ω differential pair.
Important Design Decisions
MP2315S variant has no PGOOD; rail LEDs are used.
USB is self-powered/data-only and cannot back-power board 5V.
BTS7960B remains the locked motor device despite obsolete lifecycle status.
The Flux library did not contain the exact Alpha & Omega AO4407A; AO4407A-VB is used as a pin-compatible SO-8 substitute and is explicitly documented.
Mounting holes are deferred to PCB layout because the generic schematic mounting-hole part was unavailable to instantiate.
Assumptions and Risks
AMS1117 thermal performance requires a large SOT-223 copper heat spreader and validation; a switcher would be thermally safer if sustained 3.3 V current approaches the upper estimate.
The two BTS7960 IS outputs are combined in the IBT-2-equivalent arrangement with separate 1 kΩ load resistors. In normal H-bridge drive only the active high-side device sources current sense, but simultaneous fault-current-source behavior should be validated on hardware.
The 15 A fuse may open during a prolonged 20 A motor stall; this is intentional protection but must be checked against the selected fuse curve and motor startup profile.
The current schematic connectivity is ERC-clean. Schematic symbol placement was auto-generated by the platform; a dedicated schematic-arrange API was unavailable for a final visual reflow.
Change Notes
Replaced the earlier provisional requirements with the user-locked architecture.
Completed component population and connectivity.
Added current/impedance net metadata and completed ERC remediation.