PCB Routing Status — 400 Hz Isolated PFC Power Supply
Routing Performed
- Auto-route was run on the current 180 mm × 120 mm, 4-layer placement.
- Initial route completed successfully and applied 1089 routing objects.
- A cleanup routing pass was run after removing specific problem traces.
- Targeted routing was attempted for remaining affected nets.
Router Notes
Pre-route warnings were primarily expected same-net overlapping pads on multi-pad MOSFET packages:
- Q2 multi-pad MOSFET group
- QACF1 multi-pad MOSFET group
- Q3 drain multi-pad group
- QSR1 drain multi-pad group
These are typical for high-current FET packages and were treated by the router as single electrical pins.
Current Post-Route Status
The board is partially routed but not release-clean.
Remaining checks after cleanup:
- Airwire errors remain around Q3 / ACF_SEC_FREEWHEEL multi-drain pad routing.
- Dangling trace warnings remain on several short route stubs.
- Overlapping copper errors remain, including around secondary MOSFET/pad areas and several vias/traces.
Cleanup Attempts Already Made
Removed/retried specific problem traces:
- Trace f973 / 671d class issue around ACF_SEC_FWD / ACF_SEC_FREEWHEEL
- Trace f57d / 69a1 around PFC_GATE_A_DRV
- Trace 566e / 7b06 around PFC_HV_BUS_390V
- Trace dc44 dangling stub
Targeted reroutes attempted:
- ACF_SEC_FWD: QSR1 drain group to T1 secondary
- ACF_SEC_FREEWHEEL: Q3 drain group to T1 secondary
- PFC_GATE_A_DRV: U1 GDA to RG1
- PFC_HV_BUS_390V: RHV1 to CBULK1
Some targeted traces routed successfully, but checks still report unresolved issues.
Recommended Next Actions
- Inspect Q3 and QSR1 footprints/pad definitions. The multi-drain pad groups are causing airwire and copper-overlap cleanup issues.
- Replace or edit the MOSFET footprints if the drain pad geometry is being represented as overlapping independent pads instead of a valid merged copper region.
- Clean dangling trace stubs after footprint/pad cleanup.
- Re-route the ACF secondary rectifier nets manually with wide copper pours/polygons instead of narrow traces.
- Review all primary-secondary isolation spacing after routing; the present routing is not yet safety-reviewed.
- Re-run full DRC after footprint cleanup and manual high-current routing.
Release Status
Do not release this routed PCB for fabrication yet. The schematic and placement are usable, and routing is substantially started, but the PCB requires manual high-current/power-stage routing cleanup and DRC closure.