Yes, please continue with PCB placement and auto-layout.
Place the M12 lens hole (12.5mm) centered 10mm from the top edge.
Place CN1 at the bottom edge, centered.
Place the IMX335 sensor directly under the lens hole.
Then run auto-layout for the remaining components.
Thought
159 days ago
Sorry, something went wrong. Please try again later.
Yes, please continue with PCB placement and auto-layout.
Place the M12 lens hole (12.5mm) centered 10mm from the top edge.
Place CN1 at the bottom edge, centered.
Place the IMX335 sensor directly under the lens hole.
Then run auto-layout for the remaining components.
Thought for 1 sec
159 days ago
Sorry, something went wrong. Please try again later.
Yes, please continue with PCB placement and auto-layout.
Place the M12 lens hole (12.5mm) centered 10mm from the top edge.
Place CN1 at the bottom edge, centered.
Place the IMX335 sensor directly under the lens hole.
Then run auto-layout for the remaining components.
Thought
159 days ago
Sorry, something went wrong. Please try again later.
Complete MIPI CSI-2 camera daughter board centered on the Sony IMX335LQN-C image sensor. The board accepts 3.3 V input from a 20-pin Hirose DF40C-20DP-0.4V(51) board-to-board connector and generates AVDD 2.9 V, DVDD 1.2 V, and OVDD 1.8 V locally. The sensor outputs a 2-lane MIPI CSI-2 interface plus differential clock, is controlled over I2C at address 0x1A, and uses a 24 MHz external input clock.
Architecture
Diagram
Electrical requirements
Sensor: Sony IMX335LQN-C
Video interface: 2-lane MIPI CSI-2 with one differential clock pair
Control bus: I2C target address 0x1A
Input clock: 24 MHz
Input supply: 3.3 V
Local rails: 2.9 V analog, 1.2 V digital core, 1.8 V I/O
MIPI protection: 2 x ST ECMF2-40A100N6 placed at the external connector side
Debug access: test points for I2C and key power rails
Mechanical requirements
Layout size: 20 mm x 32 mm
Stackup: 4 layers
Board thickness: 1.0 mm
MIPI target impedance: 100 ohm differential
Lens opening: 12.5 mm diameter M12 mount hole aligned over the image sensor
Design defaults
Use a solid ground plane; do not split analog and digital grounds.
Use low-capacitance ESD protection on external high-speed lines and place it close to the connector.
Provide local 100 nF decoupling at each sensor supply group plus bulk capacitance per regulator output.
Use 1.8 V pull-ups for the sensor control bus unless host-side level requirements later force translation.