MIPI CSI-2 Camera Board Design

Thought for 12 sec
Analyzing in depth.
B

bkummert

Yes, please continue with PCB placement and auto-layout.
Place the M12 lens hole (12.5mm) centered 10mm from the top edge.
Place CN1 at the bottom edge, centered.
Place the IMX335 sensor directly under the lens hole.
Then run auto-layout for the remaining components.
B

bkummert

Yes, please continue with PCB placement and auto-layout.
Place the M12 lens hole (12.5mm) centered 10mm from the top edge.
Place CN1 at the bottom edge, centered.
Place the IMX335 sensor directly under the lens hole.
Then run auto-layout for the remaining components.
B

bkummert

Yes, please continue with PCB placement and auto-layout.
Place the M12 lens hole (12.5mm) centered 10mm from the top edge.
Place CN1 at the bottom edge, centered.
Place the IMX335 sensor directly under the lens hole.
Then run auto-layout for the remaining components.
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Design Notes
Camera module architecture
Diagram



  
    
  
  
    
  
























20 pin board connector
MIPI ESD array 1
MIPI ESD array 2
IMX335 image sensor
I2C control and reset
24 MHz clock
3.3V input
2.9V LDO AVDD
1.2V LDO DVDD
1.8V LDO OVDD
Fixed requirements
  • Sensor: Sony IMX335LQN-C
  • Interface: 2-lane MIPI CSI-2 plus clock lane
  • Control bus: I2C address 0x1A
  • Input clock: 24 MHz
  • Input rail: 3.3V
  • Regulated rails: AVDD 2.9V, DVDD 1.2V, OVDD 1.8V
  • MIPI ESD: 2 x ST ECMF2-40A100N6
  • Board connector: Hirose DF40C-20DP-0.4V(51)
  • PCB target: 20 mm x 32 mm, 4 layers, 1.0 mm thickness
  • MIPI differential impedance target: 100 ohm
  • Lens mount opening: 12.5 mm diameter centered over sensor
Initial engineering defaults
  • Use a solid ground plane rather than split analog and digital grounds.
  • Put low-capacitance ESD arrays at the external connector side of the MIPI lanes.
  • Use local 100nF decoupling near each supply pin group plus bulk capacitors per LDO output.
  • Add I2C pull-ups to the 1.8V OVDD domain unless later host-level constraints require a different logic rail.
Provisional implementation risks
  • The IMX335LQN-C pin map used for schematic capture is reverse-engineered from community sources and must be verified against an official Sony or module-vendor reference before production.
  • The originally requested AP2112K-2.9TRG1 fixed LDO does not appear to exist as an orderable AP2112K variant. Use a library-available 2.9 V-capable alternative for AVDD and flag this substitution for review.
Implemented schematic status
  • The schematic is now wired using terminal-based placeholders for IMX335 and ECMF2 because the exact custom parts are not yet available in the project library.
  • Power tree implemented from CN1 3.3 V input to three rails:
    • U3 TPS79301-EP -> AVDD_2V9
    • U1 AP2112K-1.2TRG1 -> DVDD_1V2
    • U2 AP2112K-1.8TRG1 -> OVDD_1V8
  • 24 MHz oscillator output is wired to INCK and powered from OVDD_1V8.
  • I2C pullups, XCLR pullup, XMASTER strap, and TEST strap are wired.
  • Two discrete ECMF2 placeholder groups were created for MIPI D0 and D1 protection. Clock lane is currently routed direct without a third ESD array.
Provisional CN1 mapping used for implementation
  • CN1 pins 1-2: 3.3 V input
  • CN1 pin 3: I2C_SDA
  • CN1 pin 4: I2C_SCL
  • CN1 pin 5: XCLR
  • CN1 pin 6: XMASTER
  • CN1 pins 7-8: CSI_D0P / CSI_D0N via ECMF2 D0 array
  • CN1 pins 9-10: CSI_D1P / CSI_D1N via ECMF2 D1 array
  • CN1 pins 11-12: CSI_CKP / CSI_CKN direct
  • CN1 pins 13-24: GND
Remaining pre-manufacturing checks
  • Confirm Hirose DF40C-20DP-0.4V(51) contact numbering and whether the library symbol's 24-pin presentation matches the intended 20-position connector usage.
  • Replace placeholder terminal implementation with proper custom IMX335LQN-C and ECMF2-40A100N6 parts when available.
  • Validate every IMX335 supply, ground, CSI, and control terminal against authoritative source data before fabrication.
  • Revisit whether MIPI clock lane also requires ESD protection based on system-level ESD requirement and available channel count.

  • Camera module architecture

  • Fixed requirements

  • Initial engineering defaults

  • Provisional implementation risks

  • Implemented schematic status

  • Provisional CN1 mapping used for implementation

  • Remaining pre-manufacturing checks