Zero-Airwire Completion Campaign
Objective
Finish the validation board from the verified 16-airwire checkpoint using regional reconstruction and explicit prototype wire links.
Authoritative starting state — 2026-09-21
- 16 airwires
- 0 redundant traces / 0 redundant groups
- Retain
GND_B14, GND_M2, rebuilt TCK/TMS, R25, the four schematic-only Host-SPI links, eight custom endpoint lands, completed MISO endpoint routing, and the MOSI FPGA escape.
- The previous 20-, 23-, 24-, 26-, and 27-airwire campaign checkpoints are historical.
Final architecture
PCB copper only
Use real PCB copper and appropriately sized vias for:
- 2V5 VCCAUX closure
- Both 3V3 closures
- Ground
- CCLK
- PROGRAMN
- DONE
- Any clock, high-current, USB differential, or regulator switching path
Fitted insulated-wire ECOs
Low-speed signals may use intentional 30-AWG insulated assembly wires:
- Host SPI MISO/MOSI/SCK/CS_N/IRQ
- SWDIO
- USB VBUS sense
- DBG_GATE_ALL
- CFG1 and CFG_CS_N
- Reset branches when local copper closure is disproportionately disruptive
Construction standard:
- Two separate top-side SMD lands near accessible copper islands.
- Short local PCB stubs only, preferably under 5 mm.
- Intentional schematic link between separately named net segments.
- Insulated wire above the PCB; the cross-board wire is not PCB copper.
- Silkscreen/assembly ID, BOM note, cut length, and continuity-test row.
Current Host-SPI implementation already uses R26/R34/R35/R38 as schematic-only links and TP5/TP9/TP11/TP14/TP25/TP26/TP27/TP28 as local custom lands.
FPGA GPIO remapping
Remap ordinary GPIO only when all of the following are proven before mutation:
- Compatible I/O bank voltage and function
- Unused ball
- Clear local escape geometry
- Reachable destination island
- Matching FPGA constraints and MCU/firmware documentation update
Never remap power, ground, or dedicated configuration pins.
Region 1 — Complete Host SPI
Retained
- MISO FPGA side:
U1:PT54A -> TP5
- MISO MCU side: existing MISO copper ->
TP9
- MOSI FPGA side:
U1:PT56B -> TP11
- MOSI MCU side:
U2:PA7 -> TP14; TP14 was relocated beside U2 and locally routed.
- IRQ MCU-side fanout was rebuilt on a new two-layer path to preserve IRQ while freeing the MOSI escape cell.
- SCK MCU/J5 branches are closed through
R65/R66 and lands TP29/TP30.
- CS_N MCU/J5 branches are closed through
R67/R68 and lands TP31/TP32.
- MISO MCU is remapped from PA6 to PB4 and connected through
R69/TP33.
- CS_N MCU is remapped from PA4 to PA15. PA4 and PA6 are intentional NC and firmware must match.
- SCK MCU partial:
TP13 -> TP26
- CS_N MCU partial:
R22 -> TP28, TP16 -> TP28
Remaining
- SCK FPGA:
TP25 -> U1:PT56A
- CS_N FPGA:
TP27 -> U1:PT58A
- IRQ: existing copper ->
U1:PT20B
Execution order
- Preserve the accepted MCU/J5 fitted-wire ECO and STM32 pin remaps.
- Verify and retain that reduction.
- Preserve MOSI on PT56B.
- Resolve SCK FPGA side by a proven GPIO remap or a materially different U1 fanout reconstruction; do not recreate the failed shared PT56A/PT56B corridor.
- Resolve CS_N FPGA side by rebuilding the exact PT58A blocking fanout or a proven legal remap.
- Resolve IRQ by a local fitted-wire endpoint or changed fanout, not an unchanged direct retry.
Region exit gate: all Host-SPI endpoints have continuity through PCB copper plus documented fitted links; no unexplained Host-SPI airwires remain.
Region 2 — Mandatory power and configuration
Scope:
2V5: VCCAUX_P15 -> VCCAUX_F15- Two 3V3 closures, including
VCCIO8_P9
- CCLK
- PROGRAMN
- DONE
- CFG1 and CFG_CS_N
Execution:
- Reserve escape cells around mandatory balls.
- Move ordinary passives/test points/vias outward as needed.
- Delete complete blocking signal branches, not isolated fragments.
- Rebuild GND/power first.
- Rebuild CCLK/PROGRAMN/DONE.
- Restore displaced ordinary signals.
- Use fitted links for CFG1/CFG_CS_N only after safe FPGA-side escape lands exist.
BGA rules:
- 0.10 mm neckdown only for the shortest ball escape.
- Transition promptly to the required width.
- Keep ordinary through-vias outside BGA pad-clearance cells.
- If mandatory power cannot escape safely with the existing through-via stackup, make an explicit HDI/via-in-pad stackup decision instead of forcing violating geometry.
Region exit gate: all mandatory copper paths closed with no shorts, invalid layers, under-connected vias, or inappropriate long neckdowns.
Region 3 — MCU/debug/reset
Scope:
U2:PB1 -> R25:P1D3:A -> FPGA_RST_N existing copper- SWDIO
- USB VBUS sense
- DBG_GATE_ALL
Execution:
- Move low-priority passives/test points where needed.
- Rebuild the R25 MCU branch as a single non-looping branch.
- Attach local wire lands to accessible traces/vias away from dense U2 pads.
- Batch remaining fitted links and assembly documentation.
Region exit gate: reset, SWD, VBUS sense, and debug continuity verified with no unexplained airwires.
Hard execution controls
- One writer modifies the board at a time.
- No global autorouter.
- No unchanged retry after a documented failure.
- Inspect geometry once per region, then execute the whole region.
- Temporary local conflicts are allowed during reconstruction; judge the completed region.
- Revert only a completed region that remains electrically unsafe.
- After each accepted region, update
current-pcb-recovery-status, current-routing-handoff, and this campaign together.
Forbidden geometries and methods
- The old dual PT56A/PT56B corridor; retain MOSI and redesign/remap SCK.
- Rejected MISO Top/Mid-Layer-5 and via-in-pad/Bottom paths.
- Board-spanning distributed component footprints.
- Centralized jumper banks with long routed legs.
- Jumper lands overlapping endpoint pads.
- Through-hole jumper placement based only on visible top-side emptiness.
- Blind Host-SPI pin selection without proven escape geometry.
- Restoring stale copper removed during reconstruction.
Quantitative release gates
Immediate next milestone
Resolve the two remaining Host-SPI FPGA-side branches (TP25 -> PT56A, TP27 -> PT58A) plus IRQ using proven FPGA pin remaps or changed U1 fanout geometry. Then proceed to mandatory power/configuration reconstruction.