Routing Completion Plan
Objective
Take the verified live board from 20 airwires to zero in one controlled ECO campaign, rather than isolated add/revert experiments.
Core decision
The remaining problem is not solved by preserving the present fanout. Existing copper, nearby passives, vias, and test points may be moved or rebuilt. Prototype wire links are acceptable for low-speed signals. Power and BGA supply escapes remain copper.
Stage A — Snapshot and regional demolition
- Use the current live state as the rollback point.
- Capture the exact 20-airwire list from
Current PCB Recovery Status.
- Select the affected U1 fanout regions and delete complete obstructing branches back to accessible endpoints—not isolated segments.
- Preserve USB protected copper, regulator power-stage geometry, oscillator routing, and unrelated completed regions.
- Do not run DRC during demolition; incomplete branches are expected.
Stage B — Route critical nets first
Install these before restoring displaced signals:
- U1 ground escape for
GND_M2 with a short neckdown and offset plane via.
2V5 VCCAUX P15/F15 escapes and plane/island connection.- Both
3V3 closures, including VCCIO8_P9.
- Dedicated configuration: CCLK, PROGRAMN, DONE.
Allowed methods:
- 0.10 mm local BGA neckdowns transitioning to wider copper.
- Exact offset through-vias where clear.
- Existing inner-layer island joins.
- Local removal and reconstruction of signal traces occupying required escape cells.
- Blind/microvia only if the selected manufacturing stackup is intentionally changed and documented.
Stage C — Restore displaced ordinary signals
Rebuild every signal branch removed in Stage A using different layers/via positions. Ordinary FPGA GPIO may be remapped to compatible unused balls if this produces a materially simpler escape; any remap requires matching FPGA constraints and MCU/firmware documentation.
Stage D — Intentional assembly wire links
Close low-speed connections that remain geometrically expensive using distributed wire links:
- Two separate non-overlapping SMD solder lands per link.
- Each land positioned beside accessible existing copper, never directly over another pad.
- Only a short local copper stub from the island to its land.
- 30-AWG insulated fitted wire between the distant lands, traveling above the PCB.
- The schematic uses an intentional 0-ohm/wire-link component so connectivity and BOM remain explicit.
- No centralized jumper bank and no large through-hole resistor footprint.
Primary candidates: reset branches, SWDIO, VBUS sense, debug gate, CFG1/CS, Host SPI signals, and other low-speed GPIO.
Stage E — Final closure
- Confirm zero airwires.
- Remove only redundant copper proven unnecessary after all intended connections exist.
- Resolve shorts, overlapping copper, invalid layers, under-connected vias, and protected-region intrusions.
- Add a jumper-wire assembly table and update FPGA constraints for remapped pins.
- Generate manufacturing outputs only after the final DRC is clean.
Campaign execution constraints
- Work by complete region, not one trace at a time.
- Maximum one geometry read per region and one final DRC per completed region.
- Do not revert at the first intermediate conflict.
- Revert only if the completed region cannot be electrically safe.
- Every progress report states: starting count, ending count, copper/components changed, and remaining blockers.
First implementation region
Rebuild the U1 region containing GND_M2, VCCIO8_P9, PT54A, PT56A, and PT56B together. Route ground and 3V3 first, then restore/close MISO, SCK, and MOSI. This coordinated ordering avoids repeatedly competing for the same BGA escape cells.