Pixhawk V6X Board Discussion

flux

현재 BOM 기준으로 IC / 반도체류만 추리면 아래와 같습니다.
커넥터, 일반 R/C, 핀헤더는 제외했습니다.

Table

구분Designator부품명MPN제조사수량용도
Power MUX ICU3TPS2121RUXRTPS2121RUXRTexas Instruments / TI1POWER1/POWER2 5V 입력 자동 선택용 power mux
CAN Transceiver ICU1, U2TJA1051TK_3,118TJA1051TK/3,118NXP2CAN1/CAN2 MCU-side TX/RX ↔ CANH/CANL 변환
MOSFETQ1AO3400AO3400YFW1Buzzer 구동용 N-channel MOSFET
USB ESD/TVS ArrayD1USBLC6-2SC6USBLC6-2SC6STMicroelectronics1USB D+/D− ESD 보호
USB ESD/TVS ArrayD4USBLC6-4SC6USBLC6-4SC6Texas Instruments Inc. / ST 계열 데이터시트 사용1USB/IO ESD 보호
CAN ESD ProtectionD2, D3PESD2CAN,215PESD2CAN,215Nexperia2CANH/CANL ESD 보호
Power TVSD8, D9SMAJ5.0ASMAJ5.0ASHIKUES2POWER1/POWER2 입력 TVS 보호
Signal / Flyback DiodeD51N4148WS-7-F1N4148WS-7-FDiodes Incorporated1Buzzer/신호 보호용 다이오드
요약하면, 현재 BOM의 IC/반도체류는 8개 그룹, 총 11개 부품 인스턴스입니다.
  • U3: 1개
  • U1/U2: 2개
  • Q1: 1개
  • D1/D4: 2개
  • D2/D3: 2개
  • D8/D9: 2개
  • D5: 1개
P

pothme

왜 해당 칩을 선정했는지, 어디 가이드문서가 있었는지 확인

flux

각 IC/반도체류별로 선정 이유와 근거 문서가 실제로 어디에 기록되어 있는지 확인하겠습니다. 회로도/BOM/프로젝트 파일/데이터시트 기준으로 구분해서, 문서 근거가 없는 것은 ‘설계자 판단’으로 명확히 표시하겠습니다.
Worked for 1 min 5 sec
Thought for 8 sec
Reading the BOM for Integrated Circuit, USB, MOSFETs, ESD and Surge Protection, Diode.
Thought for a moment
Creating project documentation
I need to finalize some details and possibly create a document. The tool for filtering the BOM failed, and I had a previous list to refer to. I might consider using the full BOM without filters since it's already in context. I'll create or update a project document with the rationale for IC selection, making sure to keep it concise. It seems like I should focus only on IC and semiconductors while updating the docs.
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Schematic

Layout

3D View

USB Manual Routing Guidance
Status: USB must be manually routed before full-board autorouting.
Scope
Route only these two nets manually:
  • USB_D_P
  • USB_D_N
Do not use full-board autorouting for the USB pair. Do not route other nets until the USB pair has been manually completed and checked.
Required Route Order
The USB data path must be routed in this physical order:
  1. USB-C connector J5
  2. Primary USB ESD protection D1
  3. Additional USB protection / VBUS-related protection area D4 where applicable by net connectivity
  4. PAB/FMU interface connector J1
The intent is: connector surge enters the board, hits the ESD structure first, then continues to the FMU/PAB interface. Avoid any branch or stub that lets the signal bypass ESD protection.
Geometry Rules
Use these as starting geometry for the current 4-layer stackup:

Table

ParameterRequirement
Differential impedance target90 ohm differential
Trace width0.15 mm
Pair gap0.15 mm
D+/D- length mismatchD1 -> J1with no bypass aroundD1`.
  • No long stubs exist at J5, D1, D4, or J1.
  • Route stays on top layer over continuous L2 GND.
  • Pair gap is approximately 0.15 mm.
  • Trace width is 0.15 mm.
  • D+/D- mismatch is <= 0.5 mm.
  • Via count is 0, or any vias are paired and have nearby GND stitching.
  • No USB-specific DRC errors remain.
Current Constraint State
The project already records the USB nets as:
  • Net Type: High Speed
  • Differential pair name: USB2_DP_DN
  • Bus Type: USB 2.0
  • Target impedance: 90 ohm differential
  • Impedance tolerance: +/-10%
  • Length mismatch target: <= 0.5 mm
  • Layout trace width rule: 0.15 mm
Routing Gate
Do not run full-board autorouting until the USB pair is manually routed or the user explicitly accepts routing USB with the full-board router limitations.

  • Scope

  • Required Route Order

  • Geometry Rules

  • Manual Routing Procedure in Flux

  • Validation Checklist After Manual Routing

  • Current Constraint State

  • Routing Gate