Pixhawk V6X Board Discussion

flux

현재 BOM 기준으로 IC / 반도체류만 추리면 아래와 같습니다.
커넥터, 일반 R/C, 핀헤더는 제외했습니다.

Table

구분Designator부품명MPN제조사수량용도
Power MUX ICU3TPS2121RUXRTPS2121RUXRTexas Instruments / TI1POWER1/POWER2 5V 입력 자동 선택용 power mux
CAN Transceiver ICU1, U2TJA1051TK_3,118TJA1051TK/3,118NXP2CAN1/CAN2 MCU-side TX/RX ↔ CANH/CANL 변환
MOSFETQ1AO3400AO3400YFW1Buzzer 구동용 N-channel MOSFET
USB ESD/TVS ArrayD1USBLC6-2SC6USBLC6-2SC6STMicroelectronics1USB D+/D− ESD 보호
USB ESD/TVS ArrayD4USBLC6-4SC6USBLC6-4SC6Texas Instruments Inc. / ST 계열 데이터시트 사용1USB/IO ESD 보호
CAN ESD ProtectionD2, D3PESD2CAN,215PESD2CAN,215Nexperia2CANH/CANL ESD 보호
Power TVSD8, D9SMAJ5.0ASMAJ5.0ASHIKUES2POWER1/POWER2 입력 TVS 보호
Signal / Flyback DiodeD51N4148WS-7-F1N4148WS-7-FDiodes Incorporated1Buzzer/신호 보호용 다이오드
요약하면, 현재 BOM의 IC/반도체류는 8개 그룹, 총 11개 부품 인스턴스입니다.
  • U3: 1개
  • U1/U2: 2개
  • Q1: 1개
  • D1/D4: 2개
  • D2/D3: 2개
  • D8/D9: 2개
  • D5: 1개
P

pothme

왜 해당 칩을 선정했는지, 어디 가이드문서가 있었는지 확인

flux

각 IC/반도체류별로 선정 이유와 근거 문서가 실제로 어디에 기록되어 있는지 확인하겠습니다. 회로도/BOM/프로젝트 파일/데이터시트 기준으로 구분해서, 문서 근거가 없는 것은 ‘설계자 판단’으로 명확히 표시하겠습니다.
Worked for 1 min 5 sec
Thought for 8 sec
Reading the BOM for Integrated Circuit, USB, MOSFETs, ESD and Surge Protection, Diode.
Thought for a moment
Creating project documentation
I need to finalize some details and possibly create a document. The tool for filtering the BOM failed, and I had a previous list to refer to. I might consider using the full BOM without filters since it's already in context. I'll create or update a project document with the rationale for IC selection, making sure to keep it concise. It seems like I should focus only on IC and semiconductors while updating the docs.
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Schematic

Layout

Preview

Pixhawk v6X Freeze Assumptions and PCB Layout Checklist
Status: schematic freeze assumptions and next-stage PCB layout checklist.
No PCB placement or routing has been started from this document.
1. External I2C pull-up ownership
The schematic currently exposes these I2C buses:

Table

BusNetsConnector / usePull-up ownership assumption
GPS1 I2CI2C1_SCL_GPS1, I2C1_SDA_GPS1GPS1 full 10-pin connector J11Pull-ups may be provided by the core board or GPS module. Baseboard pull-ups are not populated in the current schematic.
GPS2 I2CI2C2_SCL_GPS2, I2C2_SDA_GPS2GPS2 connector J12Pull-ups may be provided by the core board or GPS/external module. Baseboard pull-ups are not populated in the current schematic.
External I2CI2C3_SCL_EXTERNAL1, I2C3_SDA_EXTERNAL1External I2C connector J13Pull-ups may be provided by the core board or external module. Baseboard pull-ups are not populated in the current schematic.
Freeze assumption:
  • The baseboard schematic is frozen with no dedicated I2C pull-up resistors on GPS1, GPS2, or external I2C.
  • If strict Pixhawk compatibility or the target core board requires baseboard-owned pull-ups, add one pull-up pair per bus before PCB layout freeze.
  • Safe default if later required: add 4.7 kΩ pull-ups from each SDA/SCL net to FMU_VDD_3V3, preferably DNP/configurable for each bus to avoid duplicate pull-ups with external modules.
2. Power-module ADC-safe sense signals
Power sensing nets present in the schematic:

Table

InputRaw connector-side sense netsFiltered FMU-side netsCurrent baseboard protection/filtering
POWER1POWER1_CURRENT_IN, POWER1_VOLTAGE_INPOWER1_CURRENT_SENSE, POWER1_VOLTAGE_SENSE1 kΩ series resistors and 100 nF shunt filter capacitors
POWER2POWER2_CURRENT_IN, POWER2_VOLTAGE_INPOWER2_CURRENT_SENSE, POWER2_VOLTAGE_SENSE1 kΩ series resistors and 100 nF shunt filter capacitors
Freeze assumption:
  • POWER1 and POWER2 voltage/current sense outputs from the external Pixhawk power modules must already be scaled and protected to 0-3.3 V before reaching the FMU ADC pins.
  • The baseboard only adds light RC filtering and series protection.
  • Raw battery voltage must not be connected directly to these sense nets.
  • If an onboard battery divider/current-sense circuit is later added, it must be designed and verified before schematic re-freeze.
3. TPS2121 POWER1/POWER2 power mux approval
Approved final 5 V input mux design:
  • U3 = TPS2121RUXR
  • POWER1_5V_IN -> U3 IN1
  • POWER2_5V_IN -> U3 IN2
  • U3 OUT::1 and U3 OUT::8 -> VDD_5V_IN
  • U3 PR1 tied to POWER1_5V_IN for POWER1 priority
  • U3 CP2 grounded for automatic POWER2 fallback when POWER1 is invalid
  • U3 OV1 and U3 OV2 grounded; precision overvoltage cutoff is intentionally not implemented
  • R21 = 29.8 kΩ from ILIM to GND for approximately 3.5 A typical current limit
  • C19 = 100 nF from SS to GND for soft start/inrush control
  • Input TVS/filtering and output bulk/HF filtering are retained
Freeze assumption:
  • TPS2121RUXR is approved as the final POWER1/POWER2 5 V input mux for this schematic.
  • At 3 A, final performance is layout-sensitive and requires short/wide copper and thermal spreading.
4. PCB status
Current project status:
  • Schematic: ready for freeze.
  • ERC: no electrical errors/warnings found in the latest review.
  • PCB placement: not started.
  • PCB routing: not started.
  • DRC airwires: expected because the board is not placed/routed.
  • Fabrication readiness: not ready.
Freeze assumption:
  • The project may proceed from schematic freeze to PCB layout planning only after the user explicitly confirms.
  • The design is not ready for manufacturing export until layout, placement, routing, and final DRC are complete.
PCB layout checklist
A. Pre-layout gates
  • Confirm schematic freeze is accepted.
  • Confirm final board outline / mechanical size constraints.
  • Confirm connector edge placement requirements for USB-C, POWER1/POWER2, TELEM, GPS, CAN, I2C, SPI, PWM/servo, RC, and debug connectors.
  • Confirm whether any I2C pull-ups should be added before layout.
  • Confirm whether ADC sense signals are guaranteed 0-3.3 V from the external power modules.
  • Confirm servo rail current expectation and whether servo power enters through the servo rail only.
B. Stackup and rules
  • Use at least a 4-layer stackup because the design includes USB 2.0, multiple power rails, dense PAB connectors, and 3 A power path requirements.
  • Assign a solid GND reference plane.
  • Define controlled-impedance routing for USB 2.0 D+/D- at 90 Ω differential.
  • Define wider copper/trace rules for POWER1_5V_IN, POWER2_5V_IN, VDD_5V_IN, VDD_5V_PERIPH, SERVO_VPLUS, and GND returns.
  • Define clearance/ESD constraints around exposed connectors.
C. Placement checklist
  • Place PAB connectors J1/J2 first according to mechanical/core-board constraints.
  • Place POWER1/POWER2 connectors near TPS2121 power block.
  • Place U3 TPS2121RUXR, C13/C14/C15/C16/C17/C18/C19, R21, D8/D9 tightly as a power-entry cluster.
  • Place USB-C connector on a board edge; keep D+/D- short, symmetric, and away from noisy power paths.
  • Place CAN transceivers near CAN connectors; keep TVS parts close to connector side.
  • Place TELEM/GPS/I2C/SPI connectors on accessible board edges.
  • Place PWM/servo bank as a grouped edge connector bank with clear high-current servo rail routing.
  • Place debug connector at an accessible edge but away from noisy high-current paths.
D. Routing checklist
  • Route high-current power first: POWER1/POWER2 -> TPS2121 -> VDD_5V_IN.
  • Use wide copper and thermal spreading around TPS2121 and power connectors.
  • Route GND with continuous low-impedance return paths.
  • Route USB D+/D- as a controlled-impedance differential pair with length matching and minimal stubs.
  • Route CANH/CANL as paired signals with ESD close to connectors.
  • Route ADC sense nets away from servo/power switching currents; keep RC filters near FMU/PAB side if practical.
  • Route UART/I2C/SPI away from high-current servo rail and USB where possible.
  • Route PWM/servo signals through series resistors before connector pins.
E. Post-placement / post-routing checks
  • Run DRC after placement before routing.
  • Run DRC after routing and resolve airwires, overlaps, invalid layers, dangling traces, and clearance violations.
  • Verify USB impedance/length constraints.
  • Verify TPS2121 thermal copper and power trace width.
  • Verify connector pin-1 orientation and silkscreen labels.
  • Verify no raw battery voltage is routed to ADC sense pins.
  • Verify final BOM and MPN completeness before fabrication export.

  • 1. External I2C pull-up ownership

  • 2. Power-module ADC-safe sense signals

  • 3. TPS2121 POWER1/POWER2 power mux approval

  • 4. PCB status

  • PCB layout checklist

  • A. Pre-layout gates

  • B. Stackup and rules

  • C. Placement checklist

  • D. Routing checklist

  • E. Post-placement / post-routing checks