Built the full schematic architecture around U1, PS1, U2, and U3 with mains input protection, isolated 5 V, local 3.3 V, one RTD interface, and 8 SSR control channels.
Added and wired eight SSR paths using K1-K8 plus Q1-Q8, with fused mains distribution, neutral return, and ESP32 GPIO control lines.
Added mains protection and conversion with F1, F2, RV1, and PS1.
Configured a 160 mm x 100 mm 4-layer layout with 6 mm board inset / keep-out margin for initial mains segregation and thermal routing space.
Updated Design Notes with the chosen GPIO mapping, power architecture, safety constraints, and the connector limitation.
Success criteria review
✅ The schematic now includes the required subsystems: ESP32 control, AC input power conversion, 8 SSR channels, and an RTD measurement front-end.
✅ The power tree derives isolated 5 V from mains and local 3.3 V for logic using PS1 and U2.
✅ Each SSR channel is implemented with isolated optotriac drive and a 25 A class triac device.
⚠️ The layout framework is set up for high-voltage separation, but the currently placed output/input terminal blocks U4-U13 are still placeholders and do not satisfy the final >=20 A connector requirement.
⚠️ The RTD connector U13 is presently a simplified placeholder connection, and several optional/snubber parts remain intentionally unwired, which is why ERC still reports floating pins on unfinished support parts.
Next steps
Replace U4-U13 with final >=20 A mains-rated connectors, then finish the remaining snubber / RTD support wiring and do a final ERC cleanup.
If you want, I can continue by tightening the SSR snubber network, correcting the RTD front-end to a proper 2-wire or 3-wire MAX31865 topology, and preparing the board for placement/routing.