Smart Pantry Shelf Schematic Design

flux

I checked the live ERC directly, and it currently reports 0 Floating Pin warnings on this schematic.
So I don’t have a current warning list to fix from my side. The most likely explanation is that your ERC panel is showing stale results.
Please do one of these:
  • Paste the exact 14 warning entries here, and I’ll fix them one by one.
  • Or tell me which pins the panel names, and I’ll patch only those.
I don’t want to guess and change the wrong pins if your local panel is behind the current project state.
bcheatam

bcheatam

  1. Please confirm after the fix that the Electrical Rule Check "Floating Pin" count drops to 0. Do not start PCB layout. Do not add new components. Keep all existing net names and designators unchanged except for deleting LED_3V3.

flux

Confirmed: the Electrical Rule Check Floating Pin count is now 0.
  • I did not start PCB layout.
  • I did not add any new components.
  • The LED_3V3 net is no longer present; C3 and LED1 are on 3V3.
  • Existing net names and designators were otherwise kept unchanged.
If you want, I can next do a schematic-only pass for any remaining non-floating ERC warnings.
bcheatam

bcheatam

id like to make it so my esp instead of being smd, is plugged into header pins so i have a breakout the plugs into header pins

flux

I've created a plan and started work on it.
Use female headers
Socket ESP module
Check SW2 clearance
Run ERC/DRC
Sign up to send

Files

Schematic

Layout

Preview

D1
Design Notes
Smart Pantry Shelf Master Tile
Resolved implementation decisions
  • ESP32-S3 native USB uses GPIO19 for D- and GPIO20 for D+.
  • Shared I2C bus serves the MAX17048 and MPR121 with 4.7k pull-ups to 3V3.
  • GPIO assignments chosen to avoid ESP32-S3 boot-strap conflicts where practical:
    • SDA: GPIO8
    • SCL: GPIO9
    • MPR121 IRQ: GPIO7
    • WS2812 DIN: GPIO18
    • IRQ_EXT: GPIO10
    • TILE_SEL: GPIO11
    • EN reset button on EN/CHIP_PU
    • BOOT button on GPIO0
  • Load-share topology uses a high-side PMOS between VBAT and VSYS with a 100k pull-up from gate to VSYS so the battery path is off by default. An NPN driven from VBUS pulls the PMOS gate low when USB is absent/present according to the selected topology implementation in the schematic wiring step.
Required power rails and nets
  • VBUS
  • VBAT
  • VSYS
  • 3V3
  • GND
  • D+
  • D-
  • SDA
  • SCL
  • IRQ
  • IRQ_EXT
  • TILE_SEL
  • USR_LED
  • STAT
Requirement notes
  • Battery entry must include both large solder pads labeled VBAT+ and VBAT- and a JST-PH 2-pin connector in parallel.
  • Expansion must include both a 6-pin 1.27 mm header and a separate 6-pad pogo interface carrying 3V3, GND, SDA, SCL, IRQ_EXT, TILE_SEL.
  • Schematic-only deliverable: no PCB layout work in this execution.

  • Smart Pantry Shelf Master Tile

  • Resolved implementation decisions

  • Required power rails and nets

  • Requirement notes