Schematic Error Analysis
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Download it here:
esprsso32-smart-scale-ai-auto-layout-example.pdf
What it is:
- A PDF of the project that’s easy to email or send without EDA software.
- The schematic-level confusion was cleaned up first before export.
One note: the board still has PCB routing airwires, so this PDF is fine for review/discussion, but it does not mean the PCB is fully finished for manufacturing.
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Schematic Review — 2026-05-24
Scope
This review is based only on the schematic data and datasheet-backed checks for the parts directly used in the design:
- IC1: ESP32-C3FH4
- U1: NAU7802SGI
- U2: NCP176BMX330TCG
- U3: TPS62130ARGTR
- J1: MSD-4-A microSD connector
- Y2: Johanson 2450AT18B100E antenna
High-Confidence Schematic Issues
1) ESP32 VDD_SPI is isolated instead of being powered
Observed in schematic:
- Net named
GPIO26_REDcontains only IC1:VDD_SPI and C10:P2. - This net is not tied to
PP3V3,PP3V3_L, orVDD3P3_CPU.
Why this is a real issue:
- The ESP32-C3 datasheet lists VDD_SPI as a required power pin with recommended input range 3.0 V to 3.6 V when used as an input.
- In the current schematic, that power pin is effectively left unpowered except for a capacitor.
Action:
- Connect IC1:VDD_SPI to the intended 3.3 V rail per the ESP32-C3 power scheme.
- Keep the local bypass capacitor on that rail.
- Remove the incorrect
GPIO26_REDlabeling from this net.
2) microSD SPI wiring is incorrect: MOSI is on DAT1, while CMD is left unconnected from SPI
Observed in schematic:
SPI_MISO→ J1:DAT0 (correct for SPI mode)SPI_SCK→ J1:CLK (correct for SPI mode)SPI_CS→ J1:CD/DAT3 (correct for SPI mode)SPI_MOSI→ J1:DAT1 (incorrect for SPI mode)- J1:CMD sits on a separate stray net named
GPIO26_RED
Datasheet-backed check:
- The microSD connector pin table identifies:
- CMD = command / response pin
- DAT0 = data bit 0
- CD/DAT3 = card detect / data bit 3
- DAT1 = data bit 1
- In SPI mode, the command path belongs on CMD, not DAT1.
Why this is a real issue:
- The card command/data input from the MCU is not going to the correct microSD pin.
- The card will not communicate correctly in SPI mode with the present wiring.
Action:
- Move SPI_MOSI from J1:DAT1 to J1:CMD.
- Remove the stray
GPIO26_REDnet from J1:CMD. - Leave DAT1 and DAT2 unconnected only if SPI mode is intended, and mark them clearly as unused / no-connect as appropriate.
3) NAU7802 digital supply is tied to 5 V while its interface is wired directly to a 3.3 V ESP32
Observed in schematic:
- U1:DVDD is on
PP5V0. - U1:DRDY connects directly to IC1:GPIO2.
- U1:SCLK and U1:SDIO connect to the ESP32 through pull-ups R5/R1 to PP3V3.
Datasheet-backed check:
- NAU7802 datasheet: "The digital power supply DVDD should use the same power source as used for the host processor supporting the digital interface communication."
- NAU7802 datasheet: DRDY is a CMOS high/low output.
- NAU7802 datasheet: DRDY output high ≈ 0.9 × DVDD.
- With DVDD = 5 V, DRDY high is roughly 4.5 V.
Why this is a real issue:
- DRDY can drive a voltage above the ESP32’s 3.3 V domain directly into IC1:GPIO2.
- With DVDD = 5 V, the NAU7802 input-high threshold for SCLK/SDIO also no longer matches the 3.3 V pull-up scheme cleanly.
Action:
- Move U1:DVDD from PP5V0 to PP3V3 so the ADC digital interface shares the MCU logic rail.
- Re-check DRDY, SCLK, and SDIO after that change.
4) NAU7802 clock pins are not wired as a valid crystal circuit and are not cleanly left unused
Observed in schematic:
- U1:XIN is on an unrelated stray net labeled
GPIO26_RED. - U1:XOUT is on a single-pin net
Net 28. - No valid crystal network is connected between XIN and XOUT.
Datasheet-backed check:
- NAU7802 supports an internal 4.9152 MHz RC oscillator as the power-on default clock.
- If the external crystal is used, the datasheet shows a preferred network with:
- crystal between XIN/XOUT
- 18 pF caps
- 270 Ω resistor
Why this is a real issue:
- As drawn, the external clock circuit is incomplete and invalid.
- The current
XINnet naming also falsely implies some unrelated functional signal.
Action:
- If using the internal oscillator: leave XIN/XOUT unused and explicitly mark them as no-connect.
- If using an external crystal: add the complete datasheet-recommended network and remove the stray net labels.
5) TPS62130 soft-start capacitor value does not match the datasheet application circuit
Observed in schematic:
- U3:SS/TR is connected to C26 = 4.7 µF to ground.
Datasheet-backed check:
- TPS62130 typical application uses C5 = 3.3 nF on SS/TR.
Why this is a real issue:
- The implemented value is about three orders of magnitude larger than the reference design value.
- This is not a minor tolerance difference; it materially changes startup timing behavior.
Action:
- Replace C26 4.7 µF with a value aligned to the TPS62130 soft-start design target.
- If no custom sequencing requirement exists, use the datasheet’s typical 3.3 nF starting point.
Observed in schematic:
Separate isolated nets all use the same visible name
GPIO26_RED, including at least:- U3:FB / R8 / R6
- U3:SS/TR / C26
- IC1:VDD_SPI / C10
- U1:XIN
- J1:CMD
- Y2:2
Why this is a real issue:
- The repeated name makes the schematic ambiguous and hides real errors.
- In this design, it already masks multiple unrelated problems rather than conveying a true common signal.
Action:
- Remove the reused
GPIO26_REDlabels. - Rename each net according to its actual function, for example:
- buck feedback node
- soft-start node
- VDD_SPI rail
- ADC crystal node
- Any net that is not supposed to exist should be deleted and the pin should be wired or marked no-connect.
7) Antenna pin 2 is incorrectly assigned to a named net instead of being left NC
Observed in schematic:
- Y2:2 is on a stray net named
GPIO26_RED.
Datasheet-backed check:
- Johanson 2450AT18B100 terminal configuration:
- Pin 1 = FEED
- Pin 2 = NC
Why this is a real issue:
- The schematic assigns a functional net name to a pin that the antenna datasheet defines as NC.
Action:
- Remove the net from Y2:2.
- Mark Y2:2 as no-connect.
8) Unused / floating pins are left unresolved in ERC
Observed in ERC / schematic:
Floating-pin warnings exist for:
- IC1:
MTMS,GPIO10,MTDO,XTAL_32K_P,XTAL_32K_N,SPIHD,SPIWP - U1:
VIN2P,VIN2N
Single-pin-net warnings exist for:
- U1:XOUT (
Net 28) - J1:DAT2 (
Net 30) - J1:CD (
Net 36) - plus the broken
GPIO26_REDfragments
Why this matters:
- Some of these may be intentionally unused, but the schematic does not document that intent.
- The current state leaves real faults mixed together with avoidable ERC noise.
Action:
- For intentionally unused pins, place explicit no-connect markers.
- For ESP32 internal-flash-symbol pins, use the correct symbol treatment for the actual variant or mark them appropriately.
- For optional microSD pins such as
DAT2/CD, either wire them intentionally or mark them unused. - For NAU7802 unused channel 2 inputs (
VIN2P/VIN2N), mark them no-connect if channel 2 is not used.
9) USB D+ / D− nets are not brought to a physical connector in the current schematic data
Observed in net connectivity:
USBC2.0_D_Pcontains only IC1:GPIO19 and a net label.USBC2.0_D_Ncontains only IC1:GPIO18 and a net label.- No USB connector component is present on those nets in the schematic data reviewed.
Why this is a real issue:
- The USB data interface is not actually connected off-chip in the reviewed schematic.
Action:
- If USB is required, connect GPIO18/GPIO19 to the actual USB connector/interface circuitry.
- If USB is not used, remove or relabel these dangling USB net names so the schematic reflects reality.
Lower-Severity / Documentation Issues
10) IC1 enable capacitor C2 is left as an undefined optional part
Observed in schematic:
- C2 is connected from
GPIO_ENto ground. - The part is a Generic Capacitor with value
OPTF.
Why this matters:
- The ESP32 enable node has a defined pull-up, but the RC timing/filtering intent is not actually specified.
- This leaves the reset/enable conditioning ambiguous.
Action:
- Either assign a real capacitor value or remove the part if it is not intended to be populated.
Summary of Most Critical Fixes
- Power IC1:VDD_SPI correctly.
- Rewire microSD SPI so MOSI goes to J1:CMD, not J1:DAT1.
- Move U1:DVDD to 3.3 V to match the ESP32 digital interface.
- Fix or remove the broken NAU7802 XIN/XOUT external clock wiring.
- Replace U3 SS/TR capacitor with a datasheet-appropriate value.
- Eliminate the duplicated
GPIO26_REDnet labeling.
Review Outcome
The current schematic contains real electrical design errors, not just cosmetic ERC noise. The most serious are:
- an unpowered ESP32 rail,
- a miswired microSD SPI interface, and
- a 5 V / 3.3 V digital-domain mismatch on the NAU7802-to-ESP32 interface.
Scope
High-Confidence Schematic Issues
1) **ESP32 VDD_SPI is isolated instead of being powered**
2) **microSD SPI wiring is incorrect: MOSI is on DAT1, while CMD is left unconnected from SPI**
3) **NAU7802 digital supply is tied to 5 V while its interface is wired directly to a 3.3 V ESP32**
4) **NAU7802 clock pins are not wired as a valid crystal circuit and are not cleanly left unused**
5) **TPS62130 soft-start capacitor value does not match the datasheet application circuit**
6) **The same net label `GPIO26_RED` is reused for multiple unrelated islands**
7) **Antenna pin 2 is incorrectly assigned to a named net instead of being left NC**
8) **Unused / floating pins are left unresolved in ERC**
9) **USB D+ / D− nets are not brought to a physical connector in the current schematic data**
Lower-Severity / Documentation Issues
10) **IC1 enable capacitor C2 is left as an undefined optional part**
Summary of Most Critical Fixes
Review Outcome
![ESPRSSO32 Smart Scale AI Auto Layout [Example] thumbnail](https://img-cdn.flux.ai/eyJidWNrZXQiOiJncmF2aXRvbi1lbGVjdHJpYy1zeW1ib2xzIiwia2V5IjoiZG9jdW1lbnRfYXNzZXRzL0VTUFJFU1NPMzJfU21hcnRfU2NhbGVfM0RfVGh1bW5haWwtY2QxNTI2NjItNjdjMi00MTk4LWJmNjUtNDJiZDk5N2E0ODYyLnBuZyIsImVkaXRzIjp7InJlc2l6ZSI6eyJ3aWR0aCI6MTM2LCJoZWlnaHQiOjEzNiwiZml0IjoiY29udGFpbiIsImJhY2tncm91bmQiOnsiciI6MCwiZyI6MCwiYiI6MCwiYWxwaGEiOjB9fX0sIm91dHB1dEZvcm1hdCI6IndlYnAifQ==)