Project: Chakra Brain
Engineering snapshot: 2026-09-03
Release state: Design electrically routed; manufacturing release is blocked by the items in Section 16.

1. What This Board Is

Chakra Brain is a 100 mm × 100 mm, two-layer, through-hole carrier PCB for a student robotics kit. It accepts:

one socketed 38-pin ESP32-DevKitC-VE controller module (U1),
two socketed Pololu #713 TB6612FNG dual-motor-driver modules (U2 and U3),
four custom 6P6C motor jacks (J2–J5),
one 1×8 remote-breakout socket header (J1),
separate regulated 5 V logic and nominal 8 V motor inputs (J7 and J6), and
local bulk capacitors and a 5 V indicator LED.

The carrier intentionally contains no local fuse, master switch, TVS clamp, buck regulator, or carrier-level reverse-polarity device. The external power assembly must provide regulation, current limiting/fusing, correct polarity, and safe handling of motor regenerative energy.

2. Board Construction and Verified CAD State

Table

Item	Current design value	Verification status
Board outline	100 × 100 mm rectangle	Verified in live layout
Finished stackup thickness	1.50 mm nominal	Verified in live stackup
Copper	Top + Bottom, 0.035 mm each (about 1 oz)	Verified in live stackup
Core	1.499 mm, nominal εr 4.3	Verified in live stackup
Solder mask	Top + Bottom, 0.025 mm modeled	Verified in live stackup
Silkscreen	Top + Bottom layers available; active production markings are Top Silkscreen	Verified in live layout
Standard via	0.60 mm pad / 0.30 mm drill	Verified in live stackup
Mounting holes	H1–H4, 3.20 mm NPTH at (±46, ±46) mm	Verified in live layout
Routed nets	30	Verified in schematic/layout
Route segments	201	Verified in live layout
Vias	42	Verified in live layout
Copper fills	1	Verified in live layout
Remaining airwires	0	Fresh routing-state check
Dangling traces	0	Fresh routing-state check

Routed copper widths actually present

Table

Function	Actual routed width
Logic/control and remote GPIO	0.30 mm
3V3 breakout rail	0.50 mm
Motor outputs M1–M4	1.00 mm
5V0 distribution	1.00 mm
8V motor trunk	predominantly 2.00 mm
8V capacitor branches	1.20 mm
GND	bottom copper fill with 42 stitching/transition vias and direct pad connections

The stored layout rules define 2.0 mm motor-trunk intent, 1.0 mm motor outputs, 0.8 mm 5 V intent, 0.5 mm 3.3 V intent, and 0.5 mm future logic-routing intent. Existing logic traces remain 0.30 mm because rules do not retroactively resize routed copper.

3. Component, Footprint, and Mechanical Table

“Verified” below means verified against current CAD and available manufacturer information. “Measured/controlling” means the PCB was built from a user measurement or supplied drawing and still requires a physical sample or 1:1 print check.

Table

Ref.	Item / MPN	Carrier footprint	Body/envelope and fit status
U1	Espressif ESP32-DEVKITC-VE	Two 19-pin rows, 2.54 mm longitudinal pitch, 24.75 mm measured row spacing	55 × 28 mm controlling measured module envelope; current socket footprint and 3D body were adjusted to this measurement. Physical sample fit still required.
U2, U3	Pololu #713	Two 8-pin rows, 2.54 mm pitch, 14.75 mm measured row spacing	21 × 18 mm controlling measured envelope. Current physical output/power row order is VMOT, VCC, GND, AO1, AO2, BO2, BO1, GND. Physical sample fit and orientation check still required.
J1	Samtec SSQ-108-03-G-S	1×8, 2.54 mm pitch, THT socket	Exact orderable MPN set. Pin 1 is the square pad at world X −19.11 mm; pin numbering runs right-to-left on the assembled board. Reserved external breakout keepout is 28 × 25 mm.
J2–J5	Custom 6P6C jack, PLACEHOLDER-CB-6P6C-12MM-STAGGER	Six 1.40 mm signal pads with 0.90 mm drills; two 2.30 mm mounting holes on 12.00 mm centers	Exact supplier MPN is unresolved. Current component-side relative contact centers: 1 (−1.27,0), 2 (0,+2.54), 3 (−3.81,0), 4 (−2.54,+2.54), 5 (−6.35,0), 6 (−5.08,+2.54) mm. Mounting holes: (+2.825,−2.30) and (−9.175,−2.30) mm. Must match the controlling drawing and a real sample.
J6, J7	Phoenix Contact 1729128	2-position, 5.08 mm pitch, THT	Manufacturer-rated terminal family; current layout presents wire entry at the top board edge. Verify purchased part body and screw-access direction.
C1, C2	AISHI SPZ1AM331E08O00R	Radial THT, 2.50 mm lead pitch	330 µF, 10 V, D6.3 × L8 mm. Datasheet/distributor dimensions verified.
C3	AISHI ERS1AM471E12OT	Radial THT, 2.50 mm lead pitch	470 µF, 10 V, D6.3 × L12 mm. MPN existence and dimensions verified; a dedicated Flux library part is not available.
R1	Yageo CFR-25JB-52-1K	Horizontal axial, 7.62 mm pitch, D2.5 body class	1 kΩ, ±5%, 0.25 W.
LED1	Lite-On LTL-4233	Radial THT LED footprint	Green LED; current board pads are K at (−23,17) and A at (−15.38,17) mm.
H1–H4	Custom 3.2 mm NPTH	3.20 mm drill	Excluded from BOM; intended for M3 clearance hardware.

4. External Connector Pinouts

J7 — regulated 5 V logic input

Table

Pin	Net	Function
1	5V0	Regulated +5 V input for U1, U2/U3 logic, C3, and LED1
2	GND	Common logic and motor return

Use one power method for U1 at a time. Do not simultaneously back-power U1 from USB and J7 unless the exact module power-path behavior has been verified.

J6 — nominal 8 V motor input

Table

Pin	Net	Function
1	8V_MOTOR_PROTECTED	Externally protected motor supply for U2/U3 VMOT and C1/C2
2	GND	High-current return

J1 — remote breakout socket

Top silkscreen P8…P1 is placed directly below the corresponding physical pads.

Table

Physical pin	Net	Function / restriction
1	GND	Reference ground
2	3V3	ESP32 module 3.3 V rail; use only for low-current remote loads
3	REMOTE_GPIO32	GPIO32, bidirectional 3.3 V logic
4	REMOTE_GPIO33	GPIO33, bidirectional 3.3 V logic
5	REMOTE_GPIO34	GPIO34, input only
6	REMOTE_GPIO35	GPIO35, input only
7	NC	Intentionally unconnected
8	NC	Intentionally unconnected

J1 is not Ethernet and has no magnetics, PHY, shield, or protection. External signals must remain within ESP32 3.3 V limits.

J2–J5 — motor connectors

Table

Jack	Motor	Contact 3 / board label	Contact 4 / board label	Contacts 1,2,5,6
J2	M1	M1_MOTOR_PLUS / M+ / U2 AO1	M1_MOTOR_MINUS / M− / U2 AO2	NC
J3	M2	M2_MOTOR_PLUS / M+ / U2 BO1	M2_MOTOR_MINUS / M− / U2 BO2	NC
J4	M3	M3_MOTOR_PLUS / M+ / U3 AO1	M3_MOTOR_MINUS / M− / U3 AO2	NC
J5	M4	M4_MOTOR_PLUS / M+ / U3 BO1	M4_MOTOR_MINUS / M− / U3 BO2	NC

Important: M+ and M− are net-name and wiring conventions. An H-bridge reverses instantaneous voltage polarity during reverse drive, so M+ is not permanently positive relative to M−.

5. U1 ESP32-DevKitC 38-Pin Carrier Map

Table

Pin	Module label	Carrier connection
1	3V3	J1 pin 2 / 3V3
2	EN	NC on carrier; reset/enable handled on module
3	VP / GPIO36	NC; input-only analog pin; library falsely classifies it as a power input
4	VN / GPIO39	NC; input-only analog pin
5	IO34	J1 pin 5 / REMOTE_GPIO34, input only
6	IO35	J1 pin 6 / REMOTE_GPIO35, input only
7	IO32	J1 pin 3 / REMOTE_GPIO32
8	IO33	J1 pin 4 / REMOTE_GPIO33
9	IO25	MOTOR_STBY_GPIO25 to both driver STBY pins
10	IO26	U3 BIN1 / motor M4 direction
11	IO27	U3 PWMB / motor M4 PWM
12	IO14	U2 AIN2 / motor M1 direction
13	IO12	NC
14	GND_1	GND
15	IO13	U2 AIN1 / motor M1 direction
16	D2	NC
17	D3	NC
18	CMD	NC
19	5V	5V0 from J7
20	CLK	NC
21	D0	NC
22	D1	NC
23	IO15	NC
24	IO2	NC
25	IO0	NC
26	IO4	U3 BIN2 / motor M4 direction
27	IO16	U2 PWMA / motor M1 PWM
28	IO17	U2 BIN1 / motor M2 direction
29	IO5	NC
30	IO18	U2 BIN2 / motor M2 direction
31	IO19	U2 PWMB / motor M2 PWM
32	GND_2	GND
33	IO21	U3 AIN1 / motor M3 direction
34	RX	NC
35	TX	NC
36	IO22	U3 AIN2 / motor M3 direction
37	IO23	U3 PWMA / motor M3 PWM
38	GND_3	GND

Espressif identifies VP/GPIO36, VN/GPIO39, GPIO34, and GPIO35 as input pins. The board includes a two-layer trace/via/fill keepout under the module antenna region; keep metal, batteries, cable bundles, and enclosure hardware away from that region.

6. U2 and U3 TB6612 Module Pin Maps

U2 — motors M1 and M2

Table

Pin	Signal	Net / function
1	GND	GND
2	VCC	5V0 logic supply
3	AO1	M1_MOTOR_PLUS → J2 contact 3
4	AO2	M1_MOTOR_MINUS → J2 contact 4
5	BO2	M2_MOTOR_MINUS → J3 contact 4
6	BO1	M2_MOTOR_PLUS → J3 contact 3
7	VMOT	8V_MOTOR_PROTECTED
8	GND	GND
9	GND	GND
10	PWMB	D1_PWMB_GPIO19
11	BIN2	D1_BIN2_GPIO18
12	BIN1	D1_BIN1_GPIO17
13	STBY	MOTOR_STBY_GPIO25
14	AIN1	D1_AIN1_GPIO13
15	AIN2	D1_AIN2_GPIO14
16	PWMA	D1_PWMA_GPIO16

U3 — motors M3 and M4

Table

Pin	Signal	Net / function
1	GND	GND
2	VCC	5V0 logic supply
3	AO1	M3_MOTOR_PLUS → J4 contact 3
4	AO2	M3_MOTOR_MINUS → J4 contact 4
5	BO2	M4_MOTOR_MINUS → J5 contact 4
6	BO1	M4_MOTOR_PLUS → J5 contact 3
7	VMOT	8V_MOTOR_PROTECTED
8	GND	GND
9	GND	GND
10	PWMB	D2_PWMB_GPIO27
11	BIN2	D2_BIN2_GPIO4
12	BIN1	D2_BIN1_GPIO26
13	STBY	MOTOR_STBY_GPIO25
14	AIN1	D2_AIN1_GPIO21
15	AIN2	D2_AIN2_GPIO22
16	PWMA	D2_PWMA_GPIO23

Pololu specifies VCC = 2.7–5.5 V, recommended VMOT = 4.5–13.5 V, 1 A continuous per channel, and 3 A peak per channel. The TB6612 control inputs and STBY have internal 200 kΩ pull-downs; the drivers therefore default to standby/off until STBY is driven high. The Pololu carrier includes supply filtering and motor-supply reverse-power protection, but not VCC reverse protection.

7. Passive and Mechanical Pin Connections

Table

Ref.	Pin 1	Pin 2 / other	Purpose
C1	8V_MOTOR_PROTECTED, positive	GND, negative	330 µF local motor-rail bulk near U2
C2	8V_MOTOR_PROTECTED, positive	GND, negative	330 µF local motor-rail bulk near U3
C3	5V0, positive	GND, negative	470 µF logic-rail bulk
R1	5V0	5V_POWER_LED_A	Limits LED current
LED1	K/cathode = GND	A/anode = 5V_POWER_LED_A	Green 5 V indicator
H1–H4	Mechanical only	—	3.2 mm NPTH mounting clearances

Nominal LED current is approximately (5 V − 2.1 V) / 1 kΩ = 2.9 mA. Resistor dissipation is about 8.4 mW, far below the 0.25 W rating.

8. Complete Live Netlist — All 30 Nets

Table

Net	Live endpoints
5V0	C3:1, R1:1, J7:1, U1:5V, U2:VCC, U3:VCC
5V_POWER_LED_A	R1:2, LED1:A
8V_MOTOR_PROTECTED	C1:1, C2:1, J6:1, U2:VMOT, U3:VMOT
3V3	U1:3V3, J1:2
GND	C1:2, C2:2, C3:2, LED1:K, J1:1, J6:2, J7:2, U1:GND_1/GND_2/GND_3, U2:GND pins 1/8/9, U3:GND pins 1/8/9
MOTOR_STBY_GPIO25	U1:IO25, U2:STBY, U3:STBY
D1_AIN1_GPIO13	U1:IO13, U2:AIN1
D1_AIN2_GPIO14	U1:IO14, U2:AIN2
D1_PWMA_GPIO16	U1:IO16, U2:PWMA
D1_BIN1_GPIO17	U1:IO17, U2:BIN1
D1_BIN2_GPIO18	U1:IO18, U2:BIN2
D1_PWMB_GPIO19	U1:IO19, U2:PWMB
D2_AIN1_GPIO21	U1:IO21, U3:AIN1
D2_AIN2_GPIO22	U1:IO22, U3:AIN2
D2_PWMA_GPIO23	U1:IO23, U3:PWMA
D2_BIN1_GPIO26	U1:IO26, U3:BIN1
D2_BIN2_GPIO4	U1:IO4, U3:BIN2
D2_PWMB_GPIO27	U1:IO27, U3:PWMB
REMOTE_GPIO32	U1:IO32, J1:3
REMOTE_GPIO33	U1:IO33, J1:4
REMOTE_GPIO34	U1:IO34, J1:5
REMOTE_GPIO35	U1:IO35, J1:6
M1_MOTOR_PLUS	U2:AO1, J2:3
M1_MOTOR_MINUS	U2:AO2, J2:4
M2_MOTOR_PLUS	U2:BO1, J3:3
M2_MOTOR_MINUS	U2:BO2, J3:4
M3_MOTOR_PLUS	U3:AO1, J4:3
M3_MOTOR_MINUS	U3:AO2, J4:4
M4_MOTOR_PLUS	U3:BO1, J5:3
M4_MOTOR_MINUS	U3:BO2, J5:4

9. How Current Flows

Logic path

A protected, regulated 5 V source enters J7 pin 1.
C3 provides local bulk storage between 5V0 and GND.
5V0 powers U1's 5 V input and U2/U3 VCC logic supplies.
5V0 also flows through R1 and LED1 to GND, lighting the power indicator.
U1's on-module regulator creates 3.3 V, which is exposed at J1 pin 2.
ESP32 GPIO outputs source/sink only small control currents into the TB6612 AIN/BIN/PWM/STBY inputs, referenced to common GND.

Motor path

A protected nominal 8 V source enters J6 pin 1.
The 2.0 mm trunk distributes this rail to U2/U3 VMOT; C1/C2 provide local energy storage.
For forward drive, one bridge high-side device connects VMOT to one motor output while the opposite low-side device returns the other output to GND.
Current flows through the motor winding and returns through J6 pin 2.
Reverse drive swaps the active high- and low-side devices, reversing winding current.
PWM rapidly alternates drive and recirculation states to control average motor voltage and speed.
During deceleration or external back-driving, motor energy can return to the motor rail. The upstream supply/protection must tolerate or clamp this regenerative energy.

10. Functional Operation and Firmware Startup

Apply regulated 5 V to J7 and nominal motor voltage to J6 only after polarity and continuity checks.
At reset, TB6612 control inputs and STBY are internally pulled low, so outputs default disabled.
Firmware must configure all AIN/BIN/PWM/STBY GPIOs as outputs.
Keep GPIO25/STBY low and all PWM outputs low while direction outputs are initialized.
Raise STBY only after safe states are established.
For each motor, use AIN1/AIN2 or BIN1/BIN2 for direction/brake/coast state and PWMA/PWMB for PWM speed control.
Return STBY low for an emergency software disable, but do not treat software as a substitute for the upstream fuse/master disconnect.

11. Why Each Component Is Present

Table

Component	Engineering purpose
U1	Runs firmware, Wi-Fi/BLE, remote I/O, and four motor-control channels. Socketing permits service replacement.
U2/U3	Each module provides two H-bridges, level-compatible control, internal input pull-downs, supply filtering, and motor-supply reverse-power protection.
J1	Serviceable remote breakout for GND, 3V3, and four GPIO signals.
J2–J5	Keyed motor cable interface using only center contacts 3/4.
J6	Separates high-current motor power from logic input.
J7	Accepts regulated logic power independently of the motor rail.
C1/C2	Reduce local motor-rail droop and cable-inductance transients at the driver modules.
C3	Reduces logic-rail dips that could reset the ESP32 during load steps.
R1	Limits LED1 current.
LED1	Immediate visual confirmation that 5V0 is present; it does not prove 3V3 or firmware health.
H1–H4	Mechanical mounting and serviceability.

12. Assembly and Polarity

Print the board 1:1 and place the actual U1, U2/U3, J2–J5, J6/J7, C1–C3, and J1 over their footprints.
Verify U1 24.75 mm row spacing and U2/U3 14.75 mm row spacing with calipers before ordering the PCB.
Verify the custom motor-jack contact stagger and 12 mm mounting-hole centers against the exact purchased jack.
Install low-profile socket strips and R1 first.
Install C1–C3 with pin 1/positive toward the positive rail and the negative stripe toward GND.
Install LED1 with cathode K at the square pad / GND side.
Install J6/J7 with screw access and wire entry facing the intended enclosure opening.
Inspect soldering before inserting U1/U2/U3.
Insert each module without a one-pin offset and with the correct orientation.

13. Silkscreen and Service Markings

J1 physical pins are labeled P8 through P1 below the header row.
J2–J5 physical contact 3 is labeled M+ and contact 4 M−.
J1, R1, and LED1 labels were separated to remove ambiguity.
The supplied Chakra monkey logo is implemented as real Top Silkscreen vector geometry at approximately X −47.23…−37.52 mm, Y −32.31…−24.24 mm.
“Chakra” is centered below the logo at (−43, −34.2) mm.
The raster preview does not reliably render white silkscreen; the vector PCB geometry is the verification source.

14. Electrical and Mechanical Limits

J7: regulated 5 V only. Never connect the raw 2S battery directly.
J6: intended nominal 8 V motor rail; Pololu specifies 4.5–13.5 V recommended VMOT.
U2/U3: design around 1 A continuous per channel; 3 A is a short peak rating, not a continuous operating target.
J2–J5 carry a stated 1.5 A current rating in the project. Confirm connector and cable heating at worst-case duty cycle.
C1/C2 are rated 10 V on an 8 V nominal motor rail. This is conditional on measured startup/regenerative peaks remaining below the capacitor limit; 16 V parts are preferred if mechanically compatible.
External motor and logic supplies must share GND because the control signals are not isolated.
J1 GPIO is 3.3 V only; GPIO34 and GPIO35 are input-only.
Keep the ESP32 antenna area free of copper, metal, and dense wiring.

15. Validation Evidence

Fresh checks on 2026-09-03:

0 airwires.
0 dangling traces.
No reported errors from the requested PCB checks for floating copper, overlapping copper, missing footprints, invalid layers, overlapping fills, under-connected vias, stackup validation, body overlap, pad access, edge placement, keepouts, or overlapping traces.
14 PCB warnings remain, all from intentional !important footprint/contact corrections and manufacturing exclusions.
Manufacturer-part-number check has no remaining missing-MPN errors after adding the custom-jack placeholder and exact J1 MPN.
ERC reports 18 known non-functional errors: 16 floating undefined pins plus one missing designator on the inactive Alternative Tomato Interocitor artifact, and one false U1 VP “missing power” error. U1 VP/GPIO36 is intentionally NC and is an input-only signal.

16. Manufacturing Release Blockers

The design must not be treated as a complete released manufacturing package until all items below are closed:

Custom motor jack sourcing: Replace PLACEHOLDER-CB-6P6C-12MM-STAGGER with an approved supplier/manufacturer MPN and confirm physical fit to the controlling drawing.
Automatic BOM error: Flux currently groups C1, C2, and C3 as one Generic Capacitor line, quantity 3, under SPZ1AM331E08O00R. The correct BOM is two SPZ1AM331E08O00R plus one ERS1AM471E12OT. Do not use the automatic BOM export until C3 has a dedicated part or the BOM is manually corrected.
Socket hardware BOM: Add exact orderable MPNs for two 1×19 female socket strips for U1 and four 1×8 female socket strips for U2/U3. Confirm whether module-side male headers are included with the purchased modules.
Physical sample fit: Caliper/1:1 verification is still required for the measured U1/U2/U3 row spacings and custom J2–J5 jack footprint.
Motor-rail capacitor margin: Measure worst-case motor-rail regenerative peaks or qualify 16 V replacements for C1/C2.
Inactive database artifact: The Alternative Tomato Interocitor and nested stale U3 are disabled and parked off-board, but cannot be permanently deleted with supported tooling. Final Gerber/drill visual inspection must confirm they do not export.

17. Source References

ESP32-DevKitC user guide: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-devkitc/user_guide.html
ESP32-WROVER-E module datasheet and antenna keepout: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf
Pololu #713 product/specifications: https://www.pololu.com/product/713 and https://www.pololu.com/product/713/specs
TB6612FNG datasheet: https://www.pololu.com/file/0J86/TB6612FNG.pdf
Samtec SSQ-108-03-G-S: https://www.samtec.com/products/ssq-108-03-g-s
Phoenix Contact 1729128: http://www.phoenixcontact.net/product/1729128
AISHI SPZ1AM331E08O00R product evidence: https://item.szlcsc.com/167797.html
AISHI ERS1AM471E12OT product evidence: https://robu.in/product/ers1am471e12ot-aishi-470uf-10v-%C2%B120-plugind6-3xl12mm-aluminum-electrolytic-capacitors-leaded-rohs/

1. What This Board Is
2. Board Construction and Verified CAD State
Routed copper widths actually present
3. Component, Footprint, and Mechanical Table
4. External Connector Pinouts
J7 — regulated 5 V logic input
J6 — nominal 8 V motor input
J1 — remote breakout socket
J2–J5 — motor connectors
5. U1 ESP32-DevKitC 38-Pin Carrier Map
6. U2 and U3 TB6612 Module Pin Maps
U2 — motors M1 and M2
U3 — motors M3 and M4
7. Passive and Mechanical Pin Connections
8. Complete Live Netlist — All 30 Nets
9. How Current Flows
Logic path
Motor path
10. Functional Operation and Firmware Startup
11. Why Each Component Is Present
12. Assembly and Polarity
13. Silkscreen and Service Markings
14. Electrical and Mechanical Limits
15. Validation Evidence
16. Manufacturing Release Blockers
17. Source References