# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** avdylkrasniqi - **Created:** 7/16/2025 - **Last Updated:** 7/17/2025 - **Visibility:** Public ## Key Components ### CP1 — [ESK477M025AH1AA](https://www.flux.ai/adrian95/esk477m025ah1aa~i8.md) - License: https://creativecommons.org/licenses/by/4.0/ - Manufacturer Name: Kemet - Manufacturer Part Number: ESK477M025AH1AA - Part Type: Polarized Capacitor - Datasheet URL: https://octopart.com/datasheet/esk477m025ah1aa-kemet-25533046 **Pins:** - - [pin 2] - + [pin 1] ### J10 — [XY301V-A-5.0-2P](https://www.flux.ai/jharwinbarrozo/xy301v-a-50-2p~u6.md) - Manufacturer Name: Ningbo Xinlaiya Elec. - Manufacturer Part Number: XY301V-A-5.0-2P **Pins:** - PIN1 [pin 1] - PIN2 [pin 2] ### J9 — [Pin Header 02x16 2.54mm Vertical](https://www.flux.ai/adrian95/pin-header-02x16-254mm-vertical~3q0.md) - Part Type: Connector - License: https://creativecommons.org/licenses/by/4.0/ **Pins:** - Pin_1 [pin 1] - Pin_10 [pin 10] - Pin_11 [pin 11] - Pin_12 [pin 12] - Pin_13 [pin 13] - Pin_14 [pin 14] - Pin_15 [pin 15] - Pin_16 [pin 16] - Pin_17 [pin 17] - Pin_18 [pin 18] - Pin_19 [pin 19] - Pin_2 [pin 2] - Pin_20 [pin 20] - Pin_21 [pin 21] - Pin_22 [pin 22] - Pin_23 [pin 23] - Pin_24 [pin 24] - Pin_25 [pin 25] - Pin_26 [pin 26] - Pin_27 [pin 27] - Pin_28 [pin 28] - Pin_29 [pin 29] - Pin_3 [pin 3] - Pin_30 [pin 30] - Pin_31 [pin 31] - Pin_32 [pin 32] - Pin_4 [pin 4] - Pin_5 [pin 5] - Pin_6 [pin 6] - Pin_7 [pin 7] - Pin_8 [pin 8] - Pin_9 [pin 9] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/avdylkrasniqi/2-layer-jlcpcb-constraints~ge](https://www.flux.ai/avdylkrasniqi/2-layer-jlcpcb-constraints~ge).* --- *Generated from [https://www.flux.ai/avdylkrasniqi/2-layer-jlcpcb-constraints~ge](https://www.flux.ai/avdylkrasniqi/2-layer-jlcpcb-constraints~ge)*