SMD Timer Specs
Worked for 6 mins 25 sec
Completed the documentation-only correction across all four current project files:
- Project Specification
- Functional Description
- Preliminary Component List
- Circuit Operation, Pin Map, and Test Point Guide
Recorded consistently:
- Structured readback verifies Standard 4 Layer (Custom).
- Copper layers are Top Copper, Mid-Layer 1, Mid-Layer 2, and Bottom Copper.
- Both inner layers are currently typed Signal.
- Confirming Mid-Layer 1 as solid GND reference and Mid-Layer 2 as power distribution remains a pre-routing configuration/review item.
- PCB remains unrouted.
- Auto-layout job
auto-layout-f784485f-cc4d-41ba-aa3b-00d1e6d0e7cbremainspausing.
Removed the stale two-layer discrepancy and unconfirmed-four-layer statements. No schematic or PCB data was modified.
Thought for 4 sec
Updated and reconciled all documentation, including exhaustive U1–U19 pin/net tables, complete circuit operation, AUTO/TEST sequencing, connector mappings, and practical test-point procedures:
- Project Specification
- Functional Description
- Preliminary Component List
- Circuit Operation, Pin Map, and Test Point Guide
J2 now physically matches the THT board: 90° orientation, pin 1 inward, pin 3 edgeward, with identical
ENABLE / OSC_OUT / GND ordering. The verified four-layer stackup and current unrouted/locked status are also accurately documented.Review docs and stackup
Verify layer purposes
Check connector compatibility
Try routing lock
Run design review
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Project Specification — Precision Burst Timer - SMD
Reconciled: 2026-07-24
Status: implemented schematic; placed but unrouted PCB; preliminary / release validation required.
Status: implemented schematic; placed but unrouted PCB; preliminary / release validation required.
Product intent and requirements
Battery-powered, fixed-function precision burst timer for a separate CMOS-input underwater piezo driver. Two outputs are provided:
ENABLE and gated OSC_OUT. No MCU, firmware, CPLD/FPGA, DDS, PLL, VCO, programmable memory, or programming interface is permitted. All user-visible timing derives from one 4.194304 MHz crystal.Required selections remain:
- start-to-start interval: 1, 2, 5, 10, 20, 30, 60 s;
- duration: 5, 10, 15, 20, 25, 30, 40, 50 crystal-derived ticks at 1.024 kHz;
- carrier preload P=64…419, intended
f=4,194,304/(2P)≈32.768…5.005 kHz; - AUTO periodic bursts and TEST continuous measurement mode;
OSC_OUTlow while disabled.
Current implemented schematic
Structured readback reports 100 logical schematic nets. Implemented blocks are: (1) reverse-protected always-on power plus crystal/reference division; (2) interval counting/selection; (3) duration counting/endpoint selection; and (4) carrier preload/down-count/toggle/output gating with AUTO/TEST control.
Power path is
BAT_RAW → Q14 DMP2035U-7 reverse-polarity P-MOSF → VCC_AON → Q1 BC807 switched high side → VCC_ENABLED. R31 is 1 MΩ from Q14 gate to GND. J1/J2 are 2.54 mm through-hole headers. J2 is pin 1 ENABLE, pin 2 OSC_OUT, pin 3 GND. TP1–TP10 are wired to VCC_AON, GND, MASTER_CLK, ENABLE, BURST_CLK, OSC_OUT, VCC_ENABLED, REF_32K, DUR_CLK, and SEC_CLK.The exhaustive physical-pin/net reference and functional/test procedures are maintained in the companion Functional Description.
PCB/mechanical state
- Board outline: 160 × 75 mm rectangle.
- Components are placed; routing is not complete.
- Auto-route preflight: valid, 107 PCB components and 124 PCB nets; no feasibility anomaly reported.
- Routing blocker: auto-layout job
auto-layout-f784485f-cc4d-41ba-aa3b-00d1e6d0e7cb, statuspausing. - Current checks show extensive airwires, consistent with the unrouted state.
- J1/J2: 2.54 mm through-hole headers at opposite short ends.
- J2 is intentionally THT-compatible: 01×03 vertical through-hole header, rotation 90°, center approximately (72.75, 0) mm, pin 1 inward and pin 3 nearest the right board edge. The full body is clamped inside the outline, and the square pad marks pin 1. This final orientation preserves swap-in harness/header compatibility with the THT board.
- Mounting holes: isolated plated mounting holes, not NPTH.
- Preserve two-sided product legend and switch/test-point silk labels.
Verified stackup and pre-routing plane review
Direct structured layout readback confirms Standard 4 Layer (Custom) with four copper layers: Top Copper, Mid-Layer 1, Mid-Layer 2, and Bottom Copper. The four-layer stackup is therefore verified. Current structured layer types identify both Mid-Layer 1 and Mid-Layer 2 as Signal, rather than dedicated Ground Plane / Power Plane. Before routing, assign or confirm Mid-Layer 1 as a solid GND reference and Mid-Layer 2 as power distribution, then review the resulting return paths and power topology. This documentation-only update did not modify the PCB.
Interfaces
Table
| Interface | Mapping | Implemented behavior |
|---|---|---|
| J1 | 1 BAT_RAW, 2 GND | Two-AA battery input |
| J2 | 1 ENABLE, 2 OSC_OUT, 3 GND | CMOS timing outputs to external driver |
| SW1 | 1/2/5/10/20/30/60 s | interval selector; eighth pole unused/off |
| SW2 | 5/10/15/20/25/30/40/50 ticks | duration selector |
| SW3+SW4 | P0–P11 | carrier preload selector |
| SW5 | AUTO/TEST contact network | maintained mode selector |
| TP1–TP10 | documented in Functional Description | wired production/debug access |
Electrical and performance status
Implemented connectivity is not a performance guarantee. Required prototype validation includes:
- crystal startup, frequency tolerance, temperature and aging;
- exact interval/duration/carrier timing;
- AUTO/TEST transitions and ENABLE-boundary pulse truncation;
- current in quiescent AUTO, burst, and TEST;
- power-domain backfeeding and reset behavior;
- output levels and loading at the final battery range.
Release risks / gates
- 74HC193 speed: the cited guaranteed minimum at 2.0 V is 4.0 MHz, below the required 4.194304 MHz; depleted-rail operation is not guaranteed.
- Standby current: the 1 µA aim / 10 µA ceiling is unproven; the always-on HCU oscillator may dominate.
- MOSFET/transistor leakage: Q14 leakage and switched-path leakage must be included in the standby budget.
- Prototype timing/current: final timing, current, startup, and boundary behavior require measurement.
- Routing/inner-layer configuration: board is unrouted; Standard 4 Layer (Custom) is verified, but both inner layers are still typed Signal. Mid-Layer 1 GND-reference and Mid-Layer 2 power-distribution assignment/confirmation remains required before routing.
- Manufacturing release: DRC, airwires, mechanical clearances, sourcing, and assembly files are not released.
Acceptance criteria for later release
- Standard 4 Layer (Custom) is confirmed; pre-routing review confirms Mid-Layer 1 as solid GND reference and Mid-Layer 2 as power distribution.
- All airwires routed and DRC/ERC findings resolved or justified.
- 160 × 75 mm geometry, plated holes, through-hole headers, two-sided legend, and all control/TP labels verified.
- Measurements demonstrate clock accuracy, every interval/duration/carrier selection, low inactive
OSC_OUT, AUTO/TEST operation, rail/current limits, and no harmful backfeeding. - Exact orderable parts and alternates pass datasheet, lifecycle, footprint, and sourcing review.
Change notes
- 2026-07-24 — Documentation reconciliation: updated from stale preliminary state to the current 100-net wired schematic and unrouted PCB; corrected connectors, test-point wiring, plated-hole wording, routing/preflight/lock status, and retained the unresolved live stackup discrepancy.
- 2026-07-24 — J2 orientation reconciliation: documented final SMD/THT physical alignment: 90° rotation, approximately (72.75, 0) mm, pin 1 inward, pin 3 edgeward, and square pad at pin 1; no preliminary-orientation caveat remains.
- 2026-07-24 — Stackup readback correction: replaced the stale two-layer discrepancy with verified Standard 4 Layer (Custom) readback and retained inner-plane assignment/review as a pre-routing item.
Product intent and requirements
Current implemented schematic
PCB/mechanical state
Verified stackup and pre-routing plane review
Interfaces
Electrical and performance status
Release risks / gates
Acceptance criteria for later release
Change notes
