SMD Timer Specs
I think we have a big backlog of cumulative crud here. I think we might want to go to a version 2 with same schmatic and physical layout but start fresh on routing with a big emphasis on manhattan layer approach. Can you generate a fresh new project as Precision Burst timer SMD version 2? we want identical board dimensions and connectors and component positions but ditch all the copper traces. keep documentation too. we just want a fresh start on routing. Does that sound like a good idea?
Thought for 15 sec
Yes—this is the right recovery strategy. I’ll create Precision Burst Timer SMD Version 2 as a clean project, preserve the schematic, documentation, board geometry, connectors, holes, silkscreen, and exact component placement, remove all traces/vias/copper routing, then verify the new board is ready for Manhattan routing.
Worked for 2 mins 5 sec
The new project is created: Precision Burst Timer SMD Version 2. The clean recreation is now copying the schematic, files, mechanics, labels, and exact placement while explicitly excluding every trace, via, and routed-copper artifact.
Worked for 1 min 47 sec
Yes—the Version 2 approach is appropriate.
Created Precision Burst Timer SMD Version 2 and completed the clean-recreation task intended to preserve:
- Schematic and netlist
- Project documentation
- 160 × 75 mm four-layer board
- Exact component placement and connectors
- Holes, keepouts, labels, and silkscreen
- No PCB traces or vias
- Manhattan routing requirements for the fresh routing pass
Further independent verification is pending because no ACUs remain. Before routing, verify the new project has four copper layers, matching component placement, and zero routed copper.
Check leftover routing
Compare placement
Document routing rules
Verify stackup
Preliminary Component List — Precision Burst Timer - SMD
Reconciled: 2026-07-24
Status: current implemented candidate list; preliminary / datasheet verification and release validation required. Exact MPNs are listed only where already present and verified in project metadata/BOM.
Status: current implemented candidate list; preliminary / datasheet verification and release validation required. Exact MPNs are listed only where already present and verified in project metadata/BOM.
Implemented candidate inventory
Table
| Designators | Qty | Implemented candidate / value | Package / role | Release note |
|---|---|---|---|---|
| U1 | 1 | 74HCU04D-Q100J | SO-14 unbuffered inverter oscillator | standby/startup validation required |
| U2,U3 | 2 | 74HC4040D,652 | SO-16 binary dividers | physical pin-5 library label is 3; currently NC |
| U4–U7 | 4 | 74HC4017D,653 | SO-16 decade counters | interval/duration counters |
| U8–U10 | 3 | 74HC193D,653 | SO-16 preload counters | 4.194304 MHz at 2.0 V not guaranteed |
| U11–U15 | 5 | 74HC08D,652 | SO-14 quad AND gates | fixed decode/gating |
| U16,U17 | 2 | 74HC04D,653 | SO-14 hex inverters | control/reset/buffering |
| U18,U19 | 2 | 74HC74D-Q100,118 | SO-14 dual D flip-flops | ENABLE latch and carrier toggle |
| Y1 | 1 | ECS-42-12-7SX-TR, 4.194304 MHz | SMD crystal | 12 pF nominal load; prototype trim/startup required |
| D1–D15 | 15 | BAS116-QR | SOT-23 low-leakage diode | pin 2 N.C. explicitly no-connect |
| Q1 | 1 | BC807 | SOT-23 PNP high-side switch | exact current/leakage margin pending |
| Q12,Q13 | 2 | MMBT2222ALT3G | SOT-23 NPN control/isolation | implemented candidates |
| Q14 | 1 | DMP2035U-7 | SOT-23 P-channel reverse-polarity MOSFET | leakage included in release risk |
| SW1,SW2,SW3 | 3 | GDH08S04 | 8-position SMD SPST banks | interval, duration, carrier P0–P7 |
| SW4 | 1 | CFS-0400TB | 4-position SMD SPST bank | carrier P8–P11 |
| SW5 | 1 | JS102011JCQN | SMD maintained SPDT | AUTO/TEST |
| J1 | 1 | Pin Header 02x01 2.54 mm Vertical | through-hole | battery input; no JST family assigned |
| J2 | 1 | Pin Header 01x03 2.54 mm Vertical | through-hole; 90° at ≈(72.75, 0) mm | ENABLE/OSC_OUT/GND; THT-aligned final orientation; square pad marks pin 1 |
| TP1–TP10 | 10 | Keystone 5018 | SMD loop test points | wired; excluded from BOM metadata |
| R2,R17,R20,R26,R31 | 5 | 1 MΩ | generic SMD resistor | R31 is Q14 gate pull-down |
| R18,R28 | 2 | 10 kΩ | generic SMD resistor | control/reset bias |
| R30 | 1 | 1 kΩ | generic SMD resistor | gated carrier clock path |
| R23 | 1 | 4.7 kΩ | generic SMD resistor | oscillator network |
| R3–R14,R19,R22,R24,R25,R27,R29 | 18 | 100 kΩ | generic SMD resistor | preload pulls, bias, output/control |
| C1–C19,C24 | 20 | 100 nF | generic SMD capacitor | logic decoupling/control |
| C20 | 1 | 4.7 µF | generic SMD capacitor | protected-rail bulk |
| C21,C22 | 2 | 20 pF | generic SMD capacitor | crystal load |
| C23 | 1 | 10 nF | generic SMD capacitor | reset/startup network |
Total current BOM grouping: 95 BOM elements, including 27 resistors and 24 capacitors. Mounting-hole and legend geometry are PCB primitives rather than schematic BOM items.
Implemented connectivity-specific notes
- Power: J1-1
BAT_RAW→ Q14 D → Q14 SVCC_AON→ Q1 E/C →VCC_ENABLED; R31 1 MΩ from Q14 G to GND. - Output: J2-1
ENABLE, J2-2OSC_OUT, J2-3 GND. - J2 mechanical mapping is intentionally identical in orientation to the verified THT header: 90° rotation, pin 1 inward, pin 3 nearest the right board edge, and center clamped to approximately (72.75, 0) mm so the full body remains inside the 160 × 75 mm outline. This preserves swap-in harness/header compatibility; the square pad identifies pin 1. The orientation is final, not preliminary.
- Test points: TP1
VCC_AON, TP2 GND, TP3MASTER_CLK, TP4ENABLE, TP5BURST_CLK, TP6OSC_OUT, TP7VCC_ENABLED, TP8REF_32K, TP9DUR_CLK, TP10SEC_CLK. - Connectors are 2.54 mm through-hole headers, not JST PH or any other unverified harness family.
- D1–D7 map 1/2/5/10/20/30/60 s selections; D8–D15 map 5/10/15/20/25/30/40/50 tick endpoints.
Candidate verification status
The listed active-device MPNs are copied from existing verified project metadata/BOM; no new orderable MPNs were invented. Generic resistors/capacitors still require released manufacturer series, tolerance, voltage rating, dielectric, leakage, package, and alternates. Header manufacturer/MPN, mating harness, plating, height, and retention remain open.
PCB/manufacturing status
- 160 × 75 mm board; placed but unrouted.
- Auto-route preflight is valid, but job
auto-layout-f784485f-cc4d-41ba-aa3b-00d1e6d0e7cbremainspausing. - Direct structured readback verifies Standard 4 Layer (Custom) with Top Copper, Mid-Layer 1, Mid-Layer 2, and Bottom Copper. Both inner layers are currently typed Signal; assigning or confirming Mid-Layer 1 as the solid GND reference and Mid-Layer 2 as power distribution remains a pre-routing configuration/review item. PCB data was not changed in this documentation-only task.
- Mounting holes are plated, not NPTH. Preserve two-sided legend and switch/TP silk labels.
Release validation still required
- 74HC193 guaranteed speed at 2.0 V.
- Full battery-range operation and logic thresholds.
- HCU oscillator startup and standby current.
- Q14/Q1 leakage and voltage drop.
- Crystal load/drive and timing accuracy.
- AUTO/TEST deterministic transitions, power-domain backfeeding, reset timing, and output pulse boundaries.
- Prototype timing/current measurements.
- Pre-routing inner-layer role confirmation (Mid-Layer 1 solid GND reference; Mid-Layer 2 power distribution), routing, DRC, assembly clearances, and sourcing/lifecycle review.
Change notes
- 2026-07-24 — Documentation reconciliation: replaced preliminary inventory and stale JST/unwired/zero-net statements with the current implemented candidate list, exact known MPNs, through-hole headers, Q14/R31, wired test points, and current unrouted/locked PCB status.
- 2026-07-24 — J2 orientation reconciliation: recorded final THT-compatible J2 placement/orientation and pin-1 square-pad convention without changing schematic or PCB data.
- 2026-07-24 — Stackup readback correction: recorded verified Standard 4 Layer (Custom) and four copper layers; retained inner-layer GND/power role assignment as a pre-routing review item.
Implemented candidate inventory
Implemented connectivity-specific notes
Candidate verification status
PCB/manufacturing status
Release validation still required
Change notes