SMD Timer Specs
Worked for 6 mins 25 sec
Completed the documentation-only correction across all four current project files:
- Project Specification
- Functional Description
- Preliminary Component List
- Circuit Operation, Pin Map, and Test Point Guide
Recorded consistently:
- Structured readback verifies Standard 4 Layer (Custom).
- Copper layers are Top Copper, Mid-Layer 1, Mid-Layer 2, and Bottom Copper.
- Both inner layers are currently typed Signal.
- Confirming Mid-Layer 1 as solid GND reference and Mid-Layer 2 as power distribution remains a pre-routing configuration/review item.
- PCB remains unrouted.
- Auto-layout job
auto-layout-f784485f-cc4d-41ba-aa3b-00d1e6d0e7cbremainspausing.
Removed the stale two-layer discrepancy and unconfirmed-four-layer statements. No schematic or PCB data was modified.
Thought for 4 sec
Updated and reconciled all documentation, including exhaustive U1–U19 pin/net tables, complete circuit operation, AUTO/TEST sequencing, connector mappings, and practical test-point procedures:
- Project Specification
- Functional Description
- Preliminary Component List
- Circuit Operation, Pin Map, and Test Point Guide
J2 now physically matches the THT board: 90° orientation, pin 1 inward, pin 3 edgeward, with identical
ENABLE / OSC_OUT / GND ordering. The verified four-layer stackup and current unrouted/locked status are also accurately documented.Review docs and stackup
Verify layer purposes
Check connector compatibility
Try routing lock
Run design review
Refine this doc
Ask about this doc
Functional Description — Precision Burst Timer - SMD
Status: schematic-derived implementation record; behavior not yet prototype-verified.
Reconciled: 2026-07-24.
Reconciled: 2026-07-24.
Current implemented state
The structured schematic contains 100 logical nets and the physical BOM contains 95 fitted schematic items (19 ICs, connectors, switches, test points, discretes, and passives). All statements below marked “implemented” come from the current netlist. Timing, current, and edge behavior remain preliminary until prototype validation. The PCB is 160 × 75 mm and remains unrouted. Auto-route preflight reports the board valid (107 PCB components, 124 PCB nets), but routing is blocked by auto-layout job
auto-layout-f784485f-cc4d-41ba-aa3b-00d1e6d0e7cb, status pausing.Verified stackup: direct structured readback confirms Standard 4 Layer (Custom) with four copper layers: Top Copper, Mid-Layer 1, Mid-Layer 2, and Bottom Copper. Both inner copper layers are currently typed Signal, not dedicated Ground Plane / Power Plane. Assigning or confirming Mid-Layer 1 as the solid GND reference and Mid-Layer 2 as power distribution remains a pre-routing configuration/review item. No PCB data was changed during this documentation reconciliation.
Four functional blocks
- Always-on power, oscillator, and references: J1/Q14 create
VCC_AON; U1/Y1 oscillate; U2/U3 divide the clock. - Interval timer and event selection: U4/U5 count seconds; U12 decodes tens; SW1 and D1–D7 select one event.
- Duration timer and endpoint selection: U6/U7 count
DUR_CLK; U11/U13 decode endpoints; SW2 and D8–D15 selectDURATION_END. - Carrier, mode, and output: U8–U10 preload/down-count, U19 toggles, U15 gates output, and U18/U16/U17 plus Q1/Q12/Q13 implement AUTO/TEST and power/reset control.
Power flow
BAT_RAW enters at J1-1 and Q14-3/D. Q14 DMP2035U-7 is the reverse-polarity P-channel MOSFET: Q14-2/S produces VCC_AON; Q14-1/G is REV_PROTECT_GATE, pulled to GND by R31 = 1 MΩ. Q1 BC807 is the switched high-side pass device: Q1-2/E is VCC_AON, Q1-1/B is SWITCH_PNP_BASE, and Q1-3/C produces VCC_ENABLED. Q12 drives the Q1 base path; Q13 returns the isolated duration-end clear signal. This is implemented connectivity, not a measured leakage/current guarantee.Oscillator and exact derived clocks
Y1 is a 4.194304 MHz ECS-42-12-7SX-TR crystal between
XTAL_IN and XTAL_OUT. U1 gate 1 is the unbuffered oscillator amplifier (XTAL_IN → OSC_AMP_OUT); U1 gate 2 buffers to MASTER_CLK. U2 is clocked by MASTER_CLK: U2 Q7 is REF_32K = 32.768 kHz and U2 Q11 is DUR_CLK = 1.024 kHz. U2 Q11 clocks U3; U3 Q10 is SEC_CLK = 1 Hz. MASTER_CLK_GATED_AON is U14-1Y from MASTER_CLK AND ENABLE_AUTO and drives the carrier clock path through R30 to CARRIER_CLK.Interval counter and selection
U4 counts
SEC_CLK. U4 Q1/Q2/Q5 provide 1 s, 2 s, and 5 s events. U4 carry clocks U5; U5 Q1/Q2/Q3/Q6 are decoded with U4 Q0 by U12 to form 10/20/30/60 s events. SW1 pins 1–7 receive EVENT_1S, EVENT_2S, EVENT_5S, EVENT_10S, EVENT_20S, EVENT_30S, EVENT_60S; opposite pins 16–10 feed D1–D7 anodes respectively. Diode cathodes join EVENT, which resets U4/U5 and is inverted to set the U18 latch. SW1 pin pair 8/9 is unused.Duration counter and endpoint selection
U6 counts
DUR_CLK; its carry clocks U7. U11/U13 decode DUR_UNITS_Q0/Q5 and U7 tens outputs to generate endpoint nets for 5, 10, 15, 20, 25, 30, 40, and 50 ticks. SW2 pins 1–8 receive those endpoint nets; pins 9–16 drive D8–D15 anodes. All diode cathodes join DURATION_END. At 1.024 kHz the nominal tick-derived times are 4.883, 9.766, 14.648, 19.531, 24.414, 29.297, 39.063, and 48.828 ms. Q13 translates the selected endpoint into ENABLE_CLEAR_N, clearing U18 and ending AUTO operation.Carrier preload, down-counter, toggle, and gate
SW3 selects preload bits P0–P7 and SW4 selects P8–P11. Open contacts are pulled low by R3–R14; closed contacts connect the bit to
VCC_ENABLED. U8/U9/U10 form the 12-bit down-counter. CARRIER_CLK enters U8 CPD; borrow cascades U8→U9→U10. U10 terminal-down and all three #PL pins share HALF_PERIOD_TICK, causing reload and clocking U19-1CP. U19-1D is fed by #1Q, so U19-1Q toggles on every half-period tick and is BURST_CLK. U15 gate 1 ANDs BURST_CLK with ENABLE to create OSC_OUT.For preload P, intended frequency is
f = 4,194,304/(2P) Hz. BURST_CLK is a toggle-derived approximately 50% waveform while running. OSC_OUT is forced low when disabled. The first or last output pulse can be truncated at ENABLE boundaries. These edge details require oscilloscope validation.AUTO and TEST sequence
AUTO: SW5 is not in TEST; interval event →
EVENT → EVENT_N sets U18 → ENABLE_AUTO; control logic powers Q1 and VCC_ENABLED; qualified ENABLE goes high; duration/carrier run; selected DURATION_END drives Q13 and clears U18; ENABLE, OSC_OUT, and switched power fall.TEST: SW5 pin 2 asserts
TEST_MODE; U16/U15 combine TEST with AUTO controls so ENABLE is asserted and the switched/carrier path remains active continuously for measurement. Returning to AUTO removes the override; deterministic recovery must still be verified on hardware.Connector behavior
Table
| Connector pin | Net | Behavior |
|---|---|---|
| J1-1 | BAT_RAW | Two-AA positive input before reverse-polarity MOSFET |
| J1-2 | GND | Battery return |
| J2-1 | ENABLE | CMOS valid-window output |
| J2-2 | OSC_OUT | Gated CMOS carrier output |
| J2-3 | GND | Output reference |
Both connectors are implemented as 2.54 mm through-hole headers, not JST connectors.
J2 physical orientation and compatibility
SMD J2 is intentionally aligned to the verified THT-board header orientation. The THT reference uses a 01×03, 2.54 mm vertical through-hole header at 90° rotation, with pin 1 inward and pin 3 nearest the right board edge. SMD J2 is likewise rotated 90° and clamped to center approximately (72.75, 0) mm, keeping its full body inside the 160 × 75 mm outline. Pin order remains pin 1 ENABLE, pin 2 OSC_OUT, pin 3 GND. This is a deliberate, final physical mapping—not a preliminary orientation—and preserves swap-in harness/header compatibility with the THT board. The square pad marks pin 1.
Test-point map and procedure
Table
| TP | Net | Expected observation |
|---|---|---|
| TP1 | VCC_AON | Protected battery rail, approximately battery voltage minus Q14 drop |
| TP2 | GND | Probe reference |
| TP3 | MASTER_CLK | 4.194304 MHz CMOS clock |
| TP4 | ENABLE | Low idle; high for selected duration in AUTO; high continuously in TEST |
| TP5 | BURST_CLK | Selected toggle-derived carrier, approximately 5.005–32.768 kHz while running |
| TP6 | OSC_OUT | Same carrier only while ENABLE is high; low otherwise |
| TP7 | VCC_ENABLED | Off/near 0 V idle; near VCC_AON during burst or TEST |
| TP8 | REF_32K | 32.768 kHz CMOS clock |
| TP9 | DUR_CLK | 1.024 kHz CMOS clock |
| TP10 | SEC_CLK | 1 Hz CMOS clock |
Probe grounding: connect the oscilloscope/frequency-counter ground to TP2 with the shortest practical ground spring/lead. Never use a raw crystal node for routine probing; use TP3 or TP8. Confirm the instrument ground is safe relative to the battery-powered board and any attached driver.
Suggested settings: 10× probe, ≥10 MΩ and low capacitance; DC coupling; begin at 1 V/div and adjust for the actual rail. For TP3 use 100 ns/div, ≥50 MHz bandwidth, rising-edge trigger near half rail. For TP8 use 10 µs/div; TP9 200 µs/div; TP10 200 ms/div. For TP5/TP6 use 10–50 µs/div and frequency-counter gate time 0.1–1 s. For ENABLE use 5–20 ms/div. Use single-shot acquisition in AUTO and normal/repetitive acquisition in TEST.
Bring-up/troubleshooting order: (1) power off and check J1 polarity/shorts; (2) power on with current limit and verify TP1/TP2; (3) verify TP3, then TP8, TP9, TP10 in that order; (4) select TEST and verify TP7 then TP4; (5) verify TP5 frequency against the preload formula and then TP6; (6) return to AUTO and capture TP4/TP6 to verify interval, duration, low-off state, and possible boundary truncation; (7) if no carrier, check TP7,
CARRIER_CLK, preload contacts, and HALF_PERIOD_TICK; (8) if AUTO never ends, check TP9, U6/U7 endpoint nets, DURATION_END, Q13, and ENABLE_CLEAR_N.Exhaustive U1–U19 physical-pin reference
Notation:
pin name → net (role). NC means no current net connection; it is not inferred. Inputs/outputs follow the library function.- U1 74HCU04: 1 1A→XTAL_IN (osc input); 2 1Y→OSC_AMP_OUT (osc output); 3 2A→OSC_AMP_OUT (buffer input); 4 2Y→MASTER_CLK (clock output); 5 3A→GND (unused input tied low); 6 3Y→NC (unused output); 7 GND→GND; 8 4Y→NC; 9 4A→GND; 10 5Y→NC; 11 5A→GND; 12 6Y→NC; 13 6A→GND; 14 VCC→VCC_AON.
- U2 74HC4040: 1 Q11→DUR_CLK; 2 Q5→NC; 3 Q4→NC; 4 Q6→NC; 5 library name
3→NC (label anomaly; physical Q3 in device pinout); 6 Q2→NC; 7 Q1→NC; 8 GND→GND; 9 Q0→NC; 10 #CP→MASTER_CLK; 11 MR→GND; 12 Q8→NC; 13 Q7→REF_32K; 14 Q9→NC; 15 Q10→NC; 16 VCC→VCC_AON. - U3 74HC4040: 1 Q11→NC; 2 Q5→NC; 3 Q4→NC; 4 Q6→NC; 5 library name
3→NC (same anomaly); 6 Q2→NC; 7 Q1→NC; 8 GND→GND; 9 Q0→NC; 10 #CP→DUR_CLK; 11 MR→GND; 12 Q8→NC; 13 Q7→NC; 14 Q9→NC; 15 Q10→SEC_CLK; 16 VCC→VCC_AON. - U4 74HC4017: 1 Q5→EVENT_5S; 2 Q1→EVENT_1S; 3 Q0→UNITS_Q0; 4 Q2→EVENT_2S; 5 Q6→NC; 6 Q7→NC; 7 Q3→NC; 8 GND→GND; 9 Q8→NC; 10 Q4→NC; 11 Q9→NC; 12 Q5-9→INTERVAL_CARRY; 13 ~CP1→GND; 14 CP0→SEC_CLK; 15 MR→EVENT; 16 VCC→VCC_AON.
- U5 74HC4017: 1 Q5→NC; 2 Q1→TENS_Q1; 3 Q0→NC; 4 Q2→TENS_Q2; 5 Q6→TENS_Q6; 6 Q7→NC; 7 Q3→TENS_Q3; 8 GND→GND; 9 Q8→NC; 10 Q4→NC; 11 Q9→NC; 12 Q5-9→NC; 13 ~CP1→GND; 14 CP0→INTERVAL_CARRY; 15 MR→EVENT; 16 VCC→VCC_AON.
- U6 74HC4017: 1 Q5→DUR_UNITS_Q5; 2 Q1→NC; 3 Q0→DUR_UNITS_Q0; 4 Q2→NC; 5 Q6→NC; 6 Q7→NC; 7 Q3→NC; 8 GND→GND; 9 Q8→NC; 10 Q4→NC; 11 Q9→NC; 12 Q5-9→DURATION_CARRY; 13 ~CP1→GND; 14 CP0→DUR_CLK; 15 MR→Net 1; 16 VCC→VCC_ENABLED.
- U7 74HC4017: 1 Q5→DUR_TENS_Q5; 2 Q1→DUR_TENS_Q1; 3 Q0→DUR_TENS_Q0; 4 Q2→DUR_TENS_Q2; 5 Q6→NC; 6 Q7→NC; 7 Q3→DUR_TENS_Q3; 8 GND→GND; 9 Q8→NC; 10 Q4→DUR_TENS_Q4; 11 Q9→NC; 12 Q5-9→NC; 13 ~CP1→GND; 14 CP0→DURATION_CARRY; 15 MR→Net 1; 16 VCC→VCC_ENABLED.
- U8 74HC193: 1 D1→CARRIER_P1; 2 Q1→NC; 3 Q0→NC; 4 CPD→CARRIER_CLK; 5 CPU→VCC_ENABLED; 6 Q2→NC; 7 Q3→NC; 8 GND→GND; 9 D3→CARRIER_P3; 10 D2→CARRIER_P2; 11 #PL→HALF_PERIOD_TICK; 12 #TCU→NC; 13 #TCD→CARRIER_BORROW_0; 14 MR→Net 1; 15 D0→CARRIER_P0; 16 VCC→VCC_ENABLED.
- U9 74HC193: 1 D1→CARRIER_P5; 2 Q1→NC; 3 Q0→NC; 4 CPD→CARRIER_BORROW_0; 5 CPU→VCC_ENABLED; 6 Q2→NC; 7 Q3→NC; 8 GND→GND; 9 D3→CARRIER_P7; 10 D2→CARRIER_P6; 11 #PL→HALF_PERIOD_TICK; 12 #TCU→NC; 13 #TCD→CARRIER_BORROW_1; 14 MR→Net 1; 15 D0→CARRIER_P4; 16 VCC→VCC_ENABLED.
- U10 74HC193: 1 D1→CARRIER_P9; 2 Q1→NC; 3 Q0→NC; 4 CPD→CARRIER_BORROW_1; 5 CPU→VCC_ENABLED; 6 Q2→NC; 7 Q3→NC; 8 GND→GND; 9 D3→CARRIER_P11; 10 D2→CARRIER_P10; 11 #PL→HALF_PERIOD_TICK; 12 #TCU→NC; 13 #TCD→HALF_PERIOD_TICK; 14 MR→Net 1; 15 D0→CARRIER_P8; 16 VCC→VCC_ENABLED.
- U11 74HC08: 1 1A→DUR_UNITS_Q5; 2 1B→DUR_TENS_Q2; 3 1Y→ENDPOINT_25T; 4 2A→DUR_UNITS_Q0; 5 2B→DUR_TENS_Q3; 6 2Y→ENDPOINT_30T; 7 GND→GND; 8 3Y→ENDPOINT_40T; 9 3A→DUR_UNITS_Q0; 10 3B→DUR_TENS_Q4; 11 4Y→ENDPOINT_50T; 12 4A→DUR_UNITS_Q0; 13 4B→DUR_TENS_Q5; 14 VCC→VCC_AON.
- U12 74HC08: 1 1A→UNITS_Q0; 2 1B→TENS_Q1; 3 1Y→EVENT_10S; 4 2A→UNITS_Q0; 5 2B→TENS_Q2; 6 2Y→EVENT_20S; 7 GND→GND; 8 3Y→EVENT_30S; 9 3A→UNITS_Q0; 10 3B→TENS_Q3; 11 4Y→EVENT_60S; 12 4A→UNITS_Q0; 13 4B→TENS_Q6; 14 VCC→VCC_ENABLED.
- U13 74HC08: 1 1A→DUR_UNITS_Q5; 2 1B→DUR_TENS_Q0; 3 1Y→ENDPOINT_5T; 4 2A→DUR_UNITS_Q0; 5 2B→DUR_TENS_Q1; 6 2Y→ENDPOINT_10T; 7 GND→GND; 8 3Y→ENDPOINT_15T; 9 3A→DUR_UNITS_Q5; 10 3B→DUR_TENS_Q1; 11 4Y→ENDPOINT_20T; 12 4A→DUR_UNITS_Q0; 13 4B→DUR_TENS_Q2; 14 VCC→VCC_ENABLED.
- U14 74HC08: 1 1A→MASTER_CLK; 2 1B→ENABLE_AUTO; 3 1Y→MASTER_CLK_GATED_AON; 4 2A→GND; 5 2B→GND; 6 2Y→NC; 7 GND→GND; 8 3Y→NC; 9 3A→GND; 10 3B→GND; 11 4Y→NC; 12 4A→GND; 13 4B→GND; 14 VCC→VCC_AON.
- U15 74HC08: 1 1A→BURST_CLK; 2 1B→ENABLE; 3 1Y→OSC_OUT; 4 2A→ENABLE_AUTO_N; 5 2B→TEST_MODE_N; 6 2Y→ENABLE_COMBINED_N; 7 GND→GND; 8 3Y→NC; 9 3A→GND; 10 3B→GND; 11 4Y→NC; 12 4A→GND; 13 4B→GND; 14 VCC→VCC_ENABLED.
- U16 74HC04: 1 1A→EVENT; 2 1Y→EVENT_N; 3 2A→ENABLE_AUTO; 4 2Y→ENABLE_AUTO_N; 5 3A→TEST_MODE; 6 3Y→TEST_MODE_N; 7 GND→GND; 8 4Y→ENABLE; 9 4A→ENABLE_COMBINED_N; 10 5Y→Net 8; 11 5A→GND; 12 6Y→Net 7; 13 6A→GND; 14 VCC→VCC_AON.
- U17 74HC04: 1 1A→Net 1; 2 1Y→CARRIER_RESET_N; 3 2A→GND; 4 2Y→Net 2; 5 3A→GND; 6 3Y→Net 3; 7 GND→GND; 8 4Y→Net 4; 9 4A→GND; 10 5Y→Net 5; 11 5A→GND; 12 6Y→Net 6; 13 6A→GND; 14 VCC→VCC_ENABLED.
- U18 74HC74: 1 #1RD→ENABLE_CLEAR_N; 2 1D→GND; 3 1CP→GND; 4 #1SD→EVENT_N; 5 1Q→ENABLE_AUTO; 6 #1Q→NC; 7 GND→GND; 8 #2Q→NC; 9 2Q→NC; 10 #2SD→VCC_AON; 11 2CP→GND; 12 2D→GND; 13 #2RD→VCC_AON; 14 VCC→VCC_AON.
- U19 74HC74: 1 #1RD→CARRIER_RESET_N; 2 1D→TOGGLE_FEEDBACK; 3 1CP→HALF_PERIOD_TICK; 4 #1SD→VCC_ENABLED; 5 1Q→BURST_CLK; 6 #1Q→TOGGLE_FEEDBACK; 7 GND→GND; 8 #2Q→NC; 9 2Q→NC; 10 #2SD→VCC_ENABLED; 11 2CP→GND; 12 2D→VCC_ENABLED; 13 #2RD→VCC_ENABLED; 14 VCC→VCC_ENABLED.
Other detailed pin mappings
Table
| Device | Physical pin mapping |
|---|---|
| SW5 | 1→VCC_AON (AUTO-side supply/contact); 2→TEST_MODE (common/output); 3→GND (other throw) |
| Q1 BC807 | 1 B→SWITCH_PNP_BASE; 2 E→VCC_AON; 3 C→VCC_ENABLED |
| Q12 MMBT2222A | 1 B→SWITCH_NPN_BASE; 2 E→GND; 3 C→SWITCH_SINK |
| Q13 MMBT2222A | 1 B→DURATION_END_ISO; 2 E→GND; 3 C→ENABLE_CLEAR_N |
| Q14 DMP2035U-7 | 1 G→REV_PROTECT_GATE; 2 S→VCC_AON; 3 D→BAT_RAW |
| Y1 | 1 XTAL1→XTAL_IN; 2 XTAL2→XTAL_OUT |
Selector and diode compact mapping
Table
| Selection | Source/contact | Return/contact | Diode |
|---|---|---|---|
| Interval 1/2/5/10/20/30/60 s | SW1 pins 1/2/3/4/5/6/7 | SW1 pins 16/15/14/13/12/11/10 | D1/D2/D3/D4/D5/D6/D7: pin1 A=SELECT_xS, pin3 K=EVENT |
| Duration 5/10/15/20/25/30/40/50 ticks | SW2 pins 1/2/3/4/5/6/7/8 | SW2 pins 9/10/11/12/13/14/15/16 | D8/D9/D10/D11/D12/D13/D14/D15: pin1 A=SELECT_xT, pin3 K=DURATION_END |
| Carrier P0–P7 | SW3 pins 1–8→CARRIER_P0…P7 | SW3 pins 9–16→VCC_ENABLED | no diode |
| Carrier P8–P11 | SW4 B1/B2/B3/B4→P8/P9/P10/P11 | SW4 A1/A2/A3/A4→VCC_ENABLED | no diode |
Every BAS116-QR physical pin 2 (
N.C.) is explicitly no-connect. SW1 pins 8/9 and all unlisted unused switch contacts have no functional net connection.Implementation cautions
- U2/U3 physical pin 5 is labeled
3in the library; it is currently NC. Do not silently rename it in documentation or infer a connection. - Generic nets
Net 1–Net 8remain in the implemented schematic; some are intentional tied-unused-gate/reset nodes, while several are single-pin inverter outputs. - 74HC193 guaranteed speed at 2.0 V, standby current, Q14/Q1 leakage, AUTO recovery, and final timing/current must be validated on prototypes.
Change notes
- 2026-07-24 — Documentation reconciliation: replaced preliminary/zero-net/JST/unwired-TP/routed-state claims with current schematic-derived connectivity, exhaustive IC pin mapping, test procedures, PCB preflight result, routing lock, and explicit stackup readback discrepancy.
- 2026-07-24 — J2 orientation reconciliation: recorded the final 90° SMD J2 orientation at approximately (72.75, 0) mm, THT-matching pin direction, square pin-1 pad, and swap-in harness/header compatibility.
- 2026-07-24 — Stackup readback correction: direct structured readback verified Standard 4 Layer (Custom) and all four copper layers; recorded that both inner layers remain Signal pending pre-routing GND-reference and power-distribution assignment/review.
Current implemented state
Four functional blocks
Power flow
Oscillator and exact derived clocks
Interval counter and selection
Duration counter and endpoint selection
Carrier preload, down-counter, toggle, and gate
AUTO and TEST sequence
Connector behavior
J2 physical orientation and compatibility
Test-point map and procedure
Exhaustive U1–U19 physical-pin reference
Other detailed pin mappings
Selector and diode compact mapping
Implementation cautions
Change notes
