Rev B POC Module Design

A

assnford1984

Add the remaining power-entry protection, replace the connector/jumper placeholders, update docs, and rerun ERC.

flux

I’ll add the remaining input/output protection parts, replace the backplane and CAN termination placeholders with closer exact parts if available, update the power/CAN docs, then rerun ERC.

flux

I’m blocked because the account has no available ACUs, so I can’t continue editing the schematic or running ERC right now.
Accomplished in this session:
  • Acknowledged the requested scope.
  • Set up the work plan for:
    • finding replacement parts for J_BP1 and J_CAN_TERM,
    • adding power-entry protection,
    • wiring the protected rails,
    • updating docs,
    • rerunning ERC.
Remaining work:
  • Replace J_BP1 with the exact Phoenix MC 1,5/10 3.81 mm backplane connector or best verified equivalent.
  • Replace J_CAN_TERM with an exact 2-pin jumper/header.
  • Add and wire remaining power-entry protection:
    • reverse-polarity protection,
    • PTC/fuse on +24V_LOGIC,
    • input TVS,
    • output-bank fuse on +24V_OUT_EN,
    • any required bulk/input capacitors.
  • Update the CAN/power sheet documentation and locked BOM notes.
  • Rerun ERC and resolve any actionable warnings/errors once ACUs are available.
Check ACU options
List protection parts
Show protection wiring
Draft documentation
Manual update package
Sign up to send

Files

Schematic

Layout

Preview

U_LDO1
U6
U_MCU1
C_CAN1
Capacitance
100nF
C_DIF_DI2
Capacitance
10nF
C_DIF_DI1
Capacitance
10nF
C_BUCK_OUT1
End of Life
Capacitance
22uF
C_MCU_DEC3
Capacitance
100nF
C_LDO_IN
Capacitance
1.0uF
C_BUCK_IN2
Capacitance
4.7uF
C_DIF_DI4
Capacitance
10nF
C_MCU_DEC2
Capacitance
100nF
C_NRST
Capacitance
100nF
C_CS
Capacitance
10nF
C_DIF_DI3
Capacitance
10nF
C_BUCK_OUT2
End of Life
Capacitance
22uF
C_LDO_OUT
Capacitance
1.0uF
C_BOOT1
Capacitance
100nF
C_MCU_DEC1
Capacitance
100nF
C_BUCK_IN1
Capacitance
4.7uF
D_TVS_DI3
D_DI3_REV
R_BUCK_EN
Resistance
100kΩ
R_DI4
Resistance
4.7kΩ
R_DIF_DI3
Resistance
100Ω
R_NRST_PU
Resistance
10kΩ
R_DI1_PU
Resistance
10kΩ
R_PD_DO3
Resistance
100kΩ
R_DI2_PU
Resistance
10kΩ
D_TVS_DI2
R_BUCK_FB_BOT
Resistance
10kΩ
R_DI2
Resistance
4.7kΩ
R_BOOT0_PD
Resistance
10kΩ
R_CAN_TERM
Resistance
120 Ω
D_TVS_DI1
R_CL
Resistance
800Ω
R_ADDR3_PU
Resistance
10kΩ
R_LED_DI2
Resistance
4.7kΩ
R_BUCK_PG
Resistance
100kΩ
R_DI1
Resistance
4.7kΩ
R_DI3_PU
Resistance
10kΩ
R_DI3
Resistance
4.7kΩ
R_DO4
Resistance
10kΩ
R_CS
Resistance
1kΩ
R_ADDR2_PU
Resistance
10kΩ
R_LED_DO4
Resistance
10kΩ
R_DI4_PU
Resistance
10kΩ
R_LED_DI3
Resistance
4.7kΩ
R_PD_DO1
Resistance
100kΩ
R_PD_DO2
Resistance
100kΩ
R_LED_DI4
Resistance
4.7kΩ
D_DI4_REV
R_DIF_DI1
Resistance
100Ω
R_MODULE_PRESENT
Resistance
10kΩ
R_LED_DO2
Resistance
10kΩ
R_DIF_DI2
Resistance
100Ω
D_DI1_REV
D_TVS_DI4
R_LED_DO3
Resistance
10kΩ
R_ADDR0_PU
Resistance
10kΩ
R_PD_DO4
Resistance
100kΩ
R_BUCK_FB_TOP
Resistance
56.2kΩ
R_DIF_DI4
Resistance
100Ω
R_DO1
Resistance
10kΩ
R_BUCK_RT
Resistance
6.34kΩ
R_FAULT_PU
Resistance
10kΩ
R_DO2
Resistance
10kΩ
D_DI2_REV
R_ADDR1_PU
Resistance
10kΩ
R_LED_DI1
Resistance
4.7kΩ
R_LED_DO1
Resistance
10kΩ
R_DO3
Resistance
10kΩ
J_CAN_TERM
J_SWD
U_CAN1
LED_DI3
LED_DO4
LED_DI1
LED_DO2
LED_DO3
LED_DO1
LED_DI2
LED_DI4
U_DI1
D_TVS_DO3
Not Recommended for New Designs
D_CAN_ESD
D_TVS_BANK
Not Recommended for New Designs
D_TVS_DO4
Not Recommended for New Designs
D_TVS_DO1
Not Recommended for New Designs
D_TVS_DO2
Not Recommended for New Designs
SW_ADDR
U_BUCK1
L_BUCK1
Inductance
33uH
J_DO
J_DI
J_BP1
Rev B Pinout Verification
Scope
Project: Open Modular UNO-Q PLC Rev B
This document verifies the pinout items needed before schematic capture of the Rev B combo module output and I/O sheets:
  • TPS274160BRLHR / TPS274160B smart high-side switch pinout.
  • STM32G0B1CBT6 LQFP-48 FDCAN pin options.
  • TLP293-4(GB-TP,E) SO-16 optocoupler channel pin order.
1. TPS274160B Pinout — WQFN-28 RLH
Source: TI TPS274160 datasheet, section 6 Pin Configuration and Functions, Table 6-1.

Table

PinPin NameTypeRev B Use
1EN3InputMCU DO3_CMD through 100 Ω, plus failsafe pulldown strategy.
2EN4InputMCU DO4_CMD through 100 Ω, plus failsafe pulldown strategy.
3SEHInputMCU GPIO diagnostic/current-sense channel-select high bit.
4SELInputMCU GPIO diagnostic/current-sense channel-select low bit.
5FAULT_N / FAULTOpen-drain outputMCU fault input with pullup. Imported symbol uses FAULT_N; treat as active-low global fault.
6CSOutputAnalog current-sense output to MCU ADC through 1 kΩ / 10 nF filter.
7CLOutput / current-limit setAdjustable current-limit pin. Connect per TI current-limit design; if external limit not used, TI notes connect to device GND.
8NC—No connect.
9GNDGround0V_OUT / device ground.
10THERInputThermal behavior control; set with defined strap/net after choosing auto-retry vs latch-off.
11DIAG_ENInputMCU GPIO or defined enable strap for diagnostics.
12OUT4OutputTie to DO4_OUT.
13OUT4OutputTie to DO4_OUT.
14OUT3OutputTie to DO3_OUT.
15OUT3OutputTie to DO3_OUT.
16NC—No connect.
17VSPowerTie to +24V_OUT_FUSED.
18VSPowerTie to +24V_OUT_FUSED.
19VSPowerTie to +24V_OUT_FUSED.
20VSPowerTie to +24V_OUT_FUSED.
21NC—No connect.
22OUT2OutputTie to DO2_OUT.
23OUT2OutputTie to DO2_OUT.
24OUT1OutputTie to DO1_OUT.
25OUT1OutputTie to DO1_OUT.
26GNDGround0V_OUT / device ground.
27EN1InputMCU DO1_CMD through 100 Ω, plus failsafe pulldown strategy.
28EN2InputMCU DO2_CMD through 100 Ω, plus failsafe pulldown strategy.
29PowerPAD / thermal padThermal / exposed padConnect to device ground/thermal copper strategy unless a later TI-specific layout note says otherwise.
Imported Flux part note:
  • Part UID: a0d07ba9-b913-4ce4-88da-6dad4bb6746d
  • Imported symbol pin names match the expected TPS274160B pin functions, including duplicate VS, OUTx, GND, NC, and PowerPAD.
2. STM32G0B1CBT6 LQFP-48 FDCAN1 Pin Options
Source: ST STM32G0B1 family datasheet / alternate-function table for LQFP-48.
Usable FDCAN1 pin pairs on STM32G0B1CBT6 LQFP-48:

Table

FDCAN1 SignalGPIOLQFP-48 PinAF
FDCAN1_RXPA1133AF3
FDCAN1_TXPA1234AF3
FDCAN1_RXPB847AF3
FDCAN1_TXPB948AF3
FDCAN1_RXPD038AF3
FDCAN1_TXPD139AF3
Rev B preferred assignment:
  • Use PA11 = FDCAN1_RX, LQFP-48 pin 33, AF3.
  • Use PA12 = FDCAN1_TX, LQFP-48 pin 34, AF3.
Reason:
  • Common STM32 CAN pin pair.
  • Keeps PB8/PB9 available as alternate CAN pair or for other board functions.
  • Keeps PD0/PD1 available if crystal, debug, or layout constraints force a change.
Not usable on LQFP-48 despite family-level FDCAN capability:
  • PC4/PC5 FDCAN pins are not bonded out on LQFP-48.
  • PD12/PD13 FDCAN pins are not bonded out on LQFP-48.
3. TLP293-4 SO-16 Pin Order
Source: Toshiba TLP293-4 datasheet pin configuration.

Table

ChannelInput AnodeInput CathodeOutput EmitterOutput Collector
1Pin 1Pin 2Pin 15Pin 16
2Pin 3Pin 4Pin 13Pin 14
3Pin 5Pin 6Pin 11Pin 12
4Pin 7Pin 8Pin 9Pin 10
Rev B digital-input wiring rule:
Text
DIx_FIELD -> input resistor -> TLP293-4 anode
TLP293-4 cathode -> DI_COM
TLP293-4 collector -> DIx_LOGIC with 10 kΩ pullup to +3V3_MOD
TLP293-4 emitter -> 0V_LOGIC
This means the optocoupler logic output is active-low at DIx_LOGIC when the field input is energized.
4. Output Schematic Capture Decisions
For the first TPS274160B output schematic sheet:
  • Add U6 = TPS274160BRLHR, Flux part UID a0d07ba9-b913-4ce4-88da-6dad4bb6746d.
  • Add four 100 Ω series resistors from MCU command nets to EN1–EN4.
  • Add four 100 kΩ pulldowns from EN1–EN4 / DOx_CMD side to 0V_LOGIC for explicit failsafe bias, even though the TI device also lists internal pulldowns.
  • Tie all VS pins to +24V_OUT_FUSED.
  • Tie duplicate output pins together per channel: OUT1 pins 24/25 to DO1_OUT; OUT2 pins 22/23 to DO2_OUT; OUT3 pins 14/15 to DO3_OUT; OUT4 pins 12/13 to DO4_OUT.
  • Tie GND pins and PowerPAD to the device ground/thermal strategy.
  • Route CS through 1 kΩ with 10 nF to ground into TPS_CS_ADC.
  • Route SEL, SEH, DIAG_EN, THER, and FAULT_N to MCU GPIO/strap nets for final firmware/control decision.
  • Mark NC pins no-connect.

  • Scope

  • 1. TPS274160B Pinout — WQFN-28 RLH

  • 2. STM32G0B1CBT6 LQFP-48 FDCAN1 Pin Options

  • 3. TLP293-4 SO-16 Pin Order

  • 4. Output Schematic Capture Decisions