Текущий 80×100 мм layout всё ещё физически перегружен и даже однослойный targeted router блокируется; для order-ready в пределах вашего лимита увеличиваю плату до 120×100 мм и повторяю edge-placement/stackup.
В этом запуске я успел перечитать live layout/DRC/stackup: плата сейчас 80×100 мм, сильно перегружена, часть компонентов/отверстий выходит за габарит, DRC всё ещё показывает сотни airwires, а stackup readback остаётся некорректным — фактически внутренние GND/PWR слои не подтверждены как рабочие.
Что осталось сделать:
Пополнить ACUs — сейчас AI-функции недоступны, поэтому я не могу продолжать tool execution.
Увеличить плату до 120×100 мм в пределах вашего лимита.
Повторить placement: все разъёмы/клеммники на кромки наружу, 4 отверстия Ø3.2 по углам, antenna keepout у края.
Full first Rev A prototype preserved: PoE AG9905-MTB, RJ45/W5500 Ethernet, 9-32 V DC LMR16020 branch and ESP32-S3 Wi-Fi are populated.
Critical ERC power errors were fixed: W5500 AVDD/AGND/support, USB ESD VBUS/GND/data lines, LMR16020 VIN/EN/BOOT/RT/EP, AG9905 PoE input/output, and Ethernet data pairs.
Added reverse-blocking diode-OR parts D7 and D8 from DC buck / PoE module outputs into the system 5 V rail. This is a functional Schottky diode-OR fallback; an ideal-diode/power-mux replacement remains recommended for lower drop.
Renamed common rails to 5V_SYS and 3V3_SYS and tagged key rails as power/ground.
Board was set to 80 x 100 mm with pcbfast/JLC-style 4-layer intent and 6 mil minimum rules.
Placement was run twice and then manually cleaned for remaining overlap issues.
Routing did not complete. The available targeted router blocked on dense 80 x 100 mm placement and there is no bulk autorouter tool exposed in this run.
DRC still reports hundreds of airwires; exported Gerbers therefore are not factory-order-ready.
Stackup was requested as Top/GND/PWR/Bottom; the tool accepted a 4-layer template but the stackup readback still shows inner layers typed as Signal instead of Ground Plane / Power Plane. This must be corrected before ordering.
80 x 100 mm is very dense for 113 physical layout components; tool reports routing congestion. A larger board, more bottom-side passives, or a manual/autorouted pass is needed.
The diode-OR implementation using SS14 is safe for reverse-blocking but drops voltage; replacing D7/D8 with an ideal-diode/power-mux stage remains recommended before production.
Do Not Send to pcbfast Yet
The generated files are a snapshot/export artifact for review, not a released manufacturing package. Do not order until routing is complete and DRC has no airwires, invalid layers, missing footprints, or cross-net copper conflicts.