Pin Function Inquiry

flux

0:33

Reading docs about how to assign the GND net to pads 3 and 4 on X2 in the schematic.

I couldn’t find any Flux documentation on explicitly assigning a net to individual schematic pins. It appears that connecting a pin to GND is done by wiring the pin to a GND symbol on the schematic.
You can explore more in the Flux Documentation or ask in the Flux Community for details:
261 days
agcab

agcab

@schematic Can you tell me the functionality of U1 pin 24?
261 days

flux

0:43

Analyzing the schematic.

Reviewing the bill of materials.

Looking for "Pin description for SWCLK" in rp2040-datasheet.pdf

U1 pin 24 (SWCLK) is the Serial Wire Debug clock input for the RP2040. According to the RP2040 datasheet:

Table

PropertyDetail
NameSWCLK
Pin Number24
TypeDigital In (FT)
Power DomainIOVDD
Reset StatePull-Up
FunctionalityProvides the debug clock for the Serial Wire Debug (SWD) interface, giving external debuggers clock timing to communicate with both cores.
Source: RP2040 Datasheet, Section 5.5 “Pinout.”
SWD header search
Label SWD nets
Routing advice
External pull-up question
Decoupling capacitor
261 days
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U1
C1
Capacitance
100nF
U5
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