Continuaré desde los 348 pines flotantes, priorizando primero la plataforma digital y después los controles/protecciones de los 12 canales. Al final ejecutaré una revisión ERC independiente y solo aprobaré el layout si quedan cerrados los pines funcionales críticos.
El saneamiento sigue en ejecución sobre la plataforma digital y los 12 canales; es un pase amplio porque cada pin debe validarse contra su función real, no conectarse solo para silenciar ERC. Después haré una revisión independiente del resultado.
El pase integral de saneamiento del esquema terminó, enfocado en la plataforma digital, Ethernet/CM4, buses de audio y controles/protecciones de los 12 canales. Sin embargo, no pude leer y reconciliar el informe final ni ejecutar el ERC independiente porque se agotaron los ACUs.
Pendiente
Revisar las modificaciones realizadas por el ejecutor.
Ejecutar ERC actualizado y corregir bloqueos restantes.
Confirmar que los 12 canales mantienen la ruta analógica independiente.
Decidir si el esquema está listo para iniciar layout.
Received notification from "Completar esquema Channel Link" that it finished — picking the work back up.
El ejecutor terminó el pase de “Completar esquema Channel Link”, pero aún falta reconciliar su informe con el diseño, ejecutar el ERC actualizado y verificar las rutas críticas antes de aprobar el esquema.
No puedo continuar esa inspección porque no hay ACUs disponibles. El proyecto permanece pendiente de:
Confirmar plataforma digital, TDM, CM4, Ethernet y Wi‑Fi.
Validar controles MIC/INSTRUMENT/LINE y estados seguros.
Verificar los 12 passthroughs analógicos independientes del firmware.
Final schematic gate — architecture blocked — 2026-08-21
Result: STOPPED SAFELY / NOT READY FOR LAYOUT. No further functional wiring was added because the remaining work requires architecture substitutions that cannot be inferred safely from the parts currently present.
Blocking substitutions and decisions
1. Per-channel MIC / INSTRUMENT / LINE selection
The existing schematic hardwires the MIC candidate into the common split. The LINE and INSTRUMENT candidates are built but cannot be connected simultaneously without a real selector.
Required replacement:
Insert one verified bipolar analog selector per channel between the three candidate outputs and ADA4610 section B. Library candidate: ADG1408YRUZ (use three inputs; unused inputs remain NC only after datasheet confirmation).
Add a hardware LOCAL/REMOTE arbitration circuit. A physical maintained mode selector must directly drive the selector in LOCAL; firmware may drive it only through tri-state isolation in REMOTE. Library candidate for logic isolation: 74LVC125APW-Q100J or equivalent.
Add pull resistors that force MIC when logic is unpowered, disconnected, reset, or tri-stated.
The current direct MIC connections must be disconnected only after the selector, arbitration logic, and safe truth table are fully captured.
This cannot be closed with the currently placed components alone.
2. Physical and digital microphone gain
The current 10 kΩ THAT1512 RG resistors provide only fixed 0 dB gain. A normal digital potentiometer is not an acceptable drop-in solution for the low-ohmic 40/60 dB gain settings.
Required replacement:
Replace each fixed RG with a datasheet-calculated switched precision resistor ladder.
Use low-level signal relays or validated ±15 V analog switches whose contact/on resistance, noise and distortion remain acceptable at the minimum RG value.
Library candidates requiring bench validation: G6K-2P-Y-DC5 signal relays or ADG1414BRUZ serial SPST switches.
Physical control must remain authoritative in LOCAL; firmware control is allowed only in REMOTE with pull-defined 0 dB default.
3. Input ESD/RF and accidental phantom protection
No exact low-capacitance, phantom-tolerant professional-audio ESD protector was found in the Flux library. The available 5 V ESD arrays are not direct substitutes on lines that may encounter phantom voltage.
Required replacement/network:
Add the symmetrical THAT1512 input RF/bias network and rail clamps per channel, then separately validate equivalent balanced LINE and Hi-Z protection networks.
Select a real surge/ESD device only after pulse energy, leakage, capacitance and phantom-fault voltage are verified.
Do not connect a 5 V USB-style TVS array directly to the audio input pins.
Add connector-local RF capacitors/ferrites and complete per-IC ±15 V decoupling.
The input-protection BOM is therefore still blocked by a missing verified protector/topology.
4. ADC / XMOS digital interface
The PCM1865 analog inputs and MCLK are connected, but BCLK, LRCLK, three DOUT lanes, control bus, addresses, reset and interrupt policy are not. The XU316 pins are programmable, so assigning arbitrary pins without the selected XMOS USB Audio firmware/resource map would create a schematic that may not compile or meet timing.
Required decision:
Lock the XMOS xcore.ai USB Audio reference design/firmware configuration first.
Produce a pin-resource map for three TDM inputs, shared BCLK/LRCLK, I²C/SPI ADC control, QSPI boot, USB HS and debug.
Only then wire U601 and configure PCM1865 addresses/control straps.
5. Compute Module 4
The placed Raspberry Pi Compute Module 4 component is a family placeholder, not a production-exact SKU. The exact 4 GB + eMMC + no-onboard-Wi-Fi ordering code is not available as a separate Flux library part.
Required replacement:
Select the exact RAM/eMMC/no-wireless CM4 ordering code.
Replace or formally qualify U701 with that exact BOM identity before deciding eMMC/SD pins, boot/recovery straps and unused-interface NC markings.
Then wire all 5 V and GND pins, Ethernet pairs/LEDs, USB service/recovery, PCIe, GPIO controls, reset/global enable and required decoupling.
6. Wi-Fi card / J701
The exact u-blox M2-JODY-W3 exists commercially but is not available in the Flux library. A missing-part request was submitted. Without the exact card component/pin evidence, the remaining J701 pins cannot be safely wired or marked NC.
Required replacement:
Import/create the exact M2-JODY-W3 part from its official datasheet, or change the architecture to a different certified module that is available and revalidate PCIe/USB/power/antenna requirements.
Keep antennas connected only to the card's documented antenna connectors; do not invent PCB RF connections at J701.
ERC gate at stop point
Floating pins: 348.
Power: 0 open errors.
Shorts: 0 open errors.
Driver conflicts: 0 open errors.
Undriven nets: 0 open errors.
Single-pin nets: 0 open errors.
Pin-to-pin conflicts: 0 open errors.
The floating pins are predominantly U701, J701, U601, PCM1865 digital/control and J801, and are functional rather than legitimate NCs.
Final decision
FAILED / BLOCKED — DO NOT START LAYOUT. The current schematic cannot be truthfully closed by wiring the existing placeholders. Complete the six substitutions/decisions above, then resume schematic capture and ERC remediation.
Second audio-route pass — 2026-08-21
Result: PARTIAL / NOT READY FOR LAYOUT. A repeatable 12-channel analog/ADC path now exists with a fail-safe fixed MIC default, but safe selectable MIC/INSTRUMENT/LINE control and connector-side input protection remain incomplete.
Completed
Validated channel 01 first, then replicated the same connectivity through channels 02–12.
Wired every combo connector XLR pair to its THAT1512 and every TRS tip/ring pair to its THAT1240; TRS tip also feeds the ADA4610 Hi-Z follower candidate path.
Added one 10 kΩ gain resistor per THAT1512, giving a fixed low-risk default gain configuration.
Configured both ADA4610 sections per channel as unity followers: section A builds the instrument candidate; section B buffers the selected default MIC path and creates the analog split.
Connected each split to its THAT1646 input and to one single-ended PCM1865 input through 10 µF DC blocking, 100 Ω series resistance, and 10 nF shunt filtering.
Connected all 12 THAT1646 outputs to the 12 male XLR connectors.
Added four 1N4004 clamps per output channel to the ±15 VA rails for accidental phantom-discharge protection.
Unified input/output connector shields, XLR pin 1, and TRS sleeves on a dedicated CHASSIS net.
Marked the unused PCM1865 analog inputs and MicBias pins as intentional NC in the selected four-channel single-ended configuration.
ERC final for this pass
Floating pins: 348, reduced from 675 at the start of this pass.
Power errors: 0.
Driver conflicts: 0.
Shorts: 0.
Undriven nets: 0.
Single-pin nets: 0.
Pin-to-pin conflicts: 0.
Floating-pin families:
Table
Family / designator
Remaining
CM4 carrier U701
185
M.2 socket J701
56
XMOS U601
33
PCM1865 digital/control pins U501/U12/U13
33 total (11 each)
Ethernet MagJack J801
22
Other power/service/control devices
19
Channel input connectors, THAT1512, THAT1240, ADA4610, THAT1646, output XLRs and ADC analog inputs
0
Real blockers
Mode selection is not complete. The current fail-safe selected route is fixed to MIC. LINE and INSTRUMENT candidate paths are electrically constructed but are not yet switched into the common split. A hardware-dominant physical selector plus deterministic relay/analog-switch control is still required before claiming MIC/INSTRUMENT/LINE completion.
Input connector protection is incomplete. The THAT1512/THAT1240/Hi-Z inputs are directly connected in the logical netlist. Symmetrical series resistance, RF capacitors, ESD clamps and accidental-phantom input protection must still be added and coordinated.
Analog local decoupling is incomplete. The ±15 V rails are connected, but per-device local 100 nF bypass capacitors for every channel IC were not replicated in this pass.
Output RF network is incomplete. Phantom clamps are present, but connector-local ferrites and 100 pF-to-CHASSIS capacitors remain to be added.
Existing THAT1646 output-net labels inherited from the first pass do not correspond numerically to the physical channel mapping; connectivity is functional, but the labels need a controlled rename cleanup.
Decision: NOT APPROVED FOR LAYOUT. The 12 fixed-default MIC analog paths and 12 ADC analog inputs are now connected, but the requested selectable three-mode front end and full input/RF protection are still blockers.
Current completion pass — 2026-08-21
Overall result: PARTIAL / NOT READY FOR LAYOUT. The schematic was materially sanitized, but the full 12-channel architecture is not yet safe to approve.
Completed in this pass
Inspected the complete project structure, BOM, project specification, prior audit, existing functional groups, nets, and ERC state.
Preserved the selected high-level architecture: 12 combo inputs, separate MIC/LINE/INSTRUMENT active paths, analog-only balanced outputs, three PCM1865 ADCs, XMOS USB-audio bridge, CM4, M.2 Wi-Fi socket, Ethernet, and a 24 V power tree.
Marked 111 explicit NC/reserved pins correctly, including THAT1646 SO16W NC pins, CM4 reserved pins, and the non-electrical terminal 7 present in the combo-connector library symbol.
Completed the ±15 V analog rail distribution from PS901 to all 12 THAT1512 preamps, 12 THAT1240 receivers, 12 ADA4610-2 op-amps, and 12 THAT1646 drivers. Connected preamp/receiver references and driver grounds to GND.
Closed the mandatory sense loops on all 12 THAT1240 receivers and all 12 THAT1646 drivers, using channel-specific net names.
Added and wired 17 support capacitors for the three PCM1865 ADCs, 24.576 MHz oscillator, and CDCLVC1104 clock fanout.
Powered all three PCM1865 devices from the existing 3.3 V audio/digital rail, connected AGND/DGND, and added VREF and internal-LDO bypass networks.
Powered and enabled the audio oscillator and clock fanout, then distributed three independent MCLK outputs to the three ADCs. Unused crystal pins and the spare fanout output were marked intentional NC.
Classified the existing supply rails as Power/Ground nets so ERC recognizes the built power tree correctly.
No PCB placement or routing was started.
ERC evidence after changes
Floating-pin findings reduced from at least 1,086 total electrical findings / 1,000+ floating-related entries to 675 floating-pin errors.
Missing power: 0 open findings after rail classification and ADC/clock power wiring.
Driver conflicts: 0 open findings.
Shorted components: 0 open findings.
Pin-to-pin conflicts: 0 open findings.
Single-pin nets: 0 open findings.
Undriven nets: 0 open findings.
No-connect misuse: 0 open findings.
Still incomplete / blocked
Twelve channel front ends: connector ESD/RFI, accidental-phantom input protection, deterministic MIC/LINE/INSTRUMENT selection, THAT1512 gain networks, Hi-Z buffering, and safe physical/digital arbitration are not captured. The existing active ICs remain mostly signal-floating.
Analog output path: THAT1646 devices have power and sense loops, but their inputs are not yet driven and their outputs are not yet connected through validated phantom-fault clamps/protection to the XLR connectors. Direct connector wiring was intentionally not done without the protection network.
ADC analog inputs: input scaling, bias/common-mode networks, anti-alias filtering, and mapping of all 12 channels into the three PCM1865 devices remain unresolved.
TDM/control: BCLK, LRCLK, three DOUT lanes, ADC control straps or serial-control bus, reset/configuration, and exact XMOS programmable-pin assignment remain unresolved.
Compute module: most CM4 carrier pins are still floating. Exact CM4 eMMC SKU, required ground/5 V pin aggregation, boot/recovery, watchdog, Ethernet magnetics wiring, USB service path, and safe unused-interface NC decisions remain pending.
Wi-Fi socket: PCIe, power, reset/clock-request, and disable are partially wired, but the exact M2-JODY-W3 module pinout must be used to classify every remaining M.2 pin. These were not mass-marked NC.
Power details: input connector/TVS and several eFuse support/control pins, analog local decoupling, rail monitoring, sequencing, and verification of regulator support values remain incomplete. Existing power converters are connected but not simulated in this pass.
Schematic legibility: functional groups exist, but the newly added passives could not be spatially arranged because no schematic-arrangement mutation tool is available in this tool set.
BOM metadata: generic-passive MPN completion remains deferred by instruction; electrical integrity is still the priority.
Decision
NOT APPROVED FOR LAYOUT. This pass removed hundreds of false/obvious floating conditions and completed safe power/clock foundations, but the remaining 675 floating pins are predominantly functional signals in the channel, ADC/TDM, CM4, M.2, Ethernet, and service/control blocks. They must be resolved by datasheet-backed block completion rather than hidden with NC markers.
Final schematic gate — architecture blocked — 2026-08-21