Hardware Logic Implementation
Scope Status
- Completed — remove abandoned MCU design: all original 26 unwired components were removed; existing project files were preserved.
- Completed — firmware-free scanner schematic: 95 components and 164 named nets, using only standard CMOS logic, analog multiplexers, displays, switches, protection, and passives.
- Completed — 55-contact adapter mapping: C01 through C55 are mapped one-to-one from three keyed 20-position headers to six mux banks.
- Completed — live decimal display: two static common-cathode seven-segment digits are driven by independent CD4511 BCD drivers and blank when no valid displayed contact exists.
- Completed — MULTIPLE behavior: a saturating 0/1/2+ frame state latches the 2+ result at the end of address 55 and resets the working state for the next frame.
- Completed — NEXT behavior: a debounced press presets ARMED; equality with the displayed address starts SEARCH; the first subsequent HIT is synchronously captured, naturally wrapping through 55 to 01.
- Completed — validation: the final ERC/design review returned no open errors or warnings for floating pins, no-connects, shorts, power pins, single-pin nets, undriven nets, driver conflicts, decoupling, capacitor voltage, or part availability.
- Unattempted — PCB layout: intentionally not started.
Selected Architecture and ICs
- U1/U2 — MC74HC160ADR2G: synchronous BCD ones/tens counters.
- U3–U8 — CD74HC4067SM: six 16:1 analog mux banks.
- U9 — 74HC138: active-low tens-bank decoder.
- U10 — 74HC574: synchronous displayed-address register.
- U11/U12 — 74HC688: displayed-address equality and fixed address-55 decode.
- U13/U14 — SN74HC14: scan oscillator, continuity Schmitt detector, debounce, and polarity conversion.
- U15–U18 — SN74HC74: frame and NEXT state storage.
- U19–U23 — 74HC08/74HC32: combinational next-state logic.
- U24/U27/U28 — 74HC157: end-of-frame state selection and synchronous display-register feedback/capture selection.
- U25/U26 — CD4511: BCD-to-seven-segment drivers.
- DS1/DS2 — HDSP-5503: common-cathode decimal digits.
No MCU, programmable logic, memory requiring programming, firmware device, CPLD, FPGA, or ASIC is present.
Scan Sequence and Timing
The counters start from 00 only during power-on/reset recovery, then scan 01, 02, …, 55, 01…. At 55, U12 asserts active-low parallel load so the next rising scan edge loads 01.
The SN74HC14 RC oscillator uses 100 kΩ and 2.2 nF. Based on typical Schmitt thresholds, the address dwell is approximately 0.17 ms, giving about 107 complete 55-address frames per second. Component and threshold tolerance will shift this value, but it remains comfortably above the required 20 frames/s and near the requested 100–500 µs dwell range.
Contact and Adapter Mapping
- J2 pins 1–20: C01–C20.
- J3 pins 1–20: C21–C40.
- J4 pins 1–15: C41–C55.
- J4 pin 16: PROBE_RETURN.
- J4 pin 17: GND / probe shield return.
- J4 pin 18: chassis/shield represented by GND.
- J4 pin 19: protected +5 V auxiliary adapter power.
- J4 pin 20: reserved, no-connect.
Mux assignment is decimal by bank: U3 handles 01–09, U4 10–19, U5 20–29, U6 30–39, U7 40–49, and U8 50–55. Ones BCD directly drives S0–S3; decoded tens BCD enables exactly one bank.
Continuity Detection
All enabled mux commons join SENSE. A 10 kΩ pull-up produces an open-circuit HIGH; the remote probe returns through 470 Ω to ground. The Schmitt input converts a selected low-resistance path into active-high HIT, with a 1 nF SENSE filter.
Using the conservative mux resistance observed during datasheet review plus 100 Ω cable/contact resistance and the 470 Ω probe limiter, the closed-loop SENSE voltage remains well below the HC14 low threshold. This supports the requested 100 Ω continuity target with substantial margin. The exact worst-case mux resistance evidence was OCR-extracted and should be reconfirmed from the manufacturer PDF before PCB release.
Display and NEXT State Behavior
When VALID is false, the first HIT is captured on the next SCAN_CLK edge into U10 and VALID becomes true. U27/U28 provide synchronous feedback-versus-scan selection, avoiding gated-clock races. The CD4511 blanking inputs follow VALID.
A NEXT press sets ARMED. ARMED remains set until the scanner reaches the currently displayed address. On that edge SEARCH is set. The first later live HIT causes CAPTURE and is loaded into the display register on the following scan edge; SEARCH then clears. If only the current contact is live, the search wraps a full frame and selects the same contact again.
If the displayed contact disappears, the end-of-frame displayed-hit state clears VALID. The display blanks and the first live hit in the next scan is acquired automatically, with less than roughly one frame of blank time.
MULTIPLE Frame Behavior
ANY_HIT records the first HIT in a frame. A later HIT at another address sets MULTI_SEEN. Because each address is visited once per frame, two events necessarily correspond to two different contact numbers. At the 55→01 edge, MULTIPLE loads the final 2+ state, while ANY_HIT and MULTI_SEEN reset for the next frame. The LED therefore shows the result of the most recently completed frame.
Power
USB-C is power-only. CC1 and CC2 each have an independent 5.1 kΩ sink pull-down. VBUS passes through a 500 mA resettable fuse to the protected +5 V rail, with a 5 V TVS and 10 µF bulk capacitor. Every IC has a dedicated 100 nF bypass capacitor. Estimated maximum steady load is below 150 mA, dominated by the static LED display.
Remaining Limitations
- This is a continuity detector, not a calibrated resistance meter; it intentionally accepts paths up to and beyond 100 Ω.
- Segment current is limited to about 2 mA nominal for conservative CD4511 loading; brightness should be checked with the selected red display in the intended enclosure lighting.
- The three keyed headers represent the motherboard adapter boundary; the mating cable-side receptacles/harness and physical 38999 adapter mechanics are outside this schematic scope.
- Project files created during the abandoned MCU attempt were preserved as requested and may contain stale historical architecture text.
- No PCB placement, routing, or mechanical connector-spacing validation was performed.