Project Start

flux

The electrical corrections are complete, but the schematic is still too scattered for a meaningful review. I’m continuing with a dedicated organization pass, then I’ll perform the final verification and stop at the schematic checkpoint.
Thought for 2 mins 5 sec
Thought for 14 sec
Thought for 10 sec
Awaiting 1 background task
"Rechargeable Fan Schematic" completed.

flux

The initial schematic draft is electrically captured with 94 components and 47 nets, including all three power stages, the finalized ATtiny404 hardware-I²C mapping, J1–J6, and TP1–TP13.
Critical review corrections completed:
  • Corrected J1 duplicated center/sleeve contacts to remove the connector-level short.
  • Connected the battery NTC into the TS network.
  • Connected DRV8833 nFAULT to ATtiny404 PB3 while preserving the approved pin map.
  • Marked unused reserved MCU pins intentionally unconnected.
Open items
  • The schematic remains visually scattered; the organization pass could not be completed because schematic-arrangement operations were unavailable.
  • ERC reports only known/justified findings:
    • U2 Vin on SYS reported undriven, although SYS is supplied by U1.
    • Three intentionally isolated J3 service-only nets.
    • One unspecified-pin warning for bidirectional TVS D4.
  • Therefore, the draft is electrically substantial but not yet ready for the requested visual review checkpoint.
No PCB layout or Gerbers were created. Execution stopped because your ACUs ran out.

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Schematic

Layout

3D View

Engineering Plan
Status: Review - awaiting approval before schematic capture or PCB work
Design Basis
  • Product: 9-inch rechargeable AC/DC fan controller PCB.
  • Adapter: external regulated 12 V, 4 A.
  • Battery: external protected 2S1P pack using two Molicel INR-18650-P28A cells, 7.2 V nominal, 8.4 V full, 2.8 Ah typical.
  • External BMS: 2S, 10 A preferred, with balancing, overcharge, overdischarge, overcurrent, and short-circuit protection.
  • Charger and power path: BQ25798RQMR, 8.4 V regulation, 2.8 A target charge current, battery NTC, simultaneous system operation and charging.
  • Motor rail: TPS63070RNMR at 6.0 V.
  • Motor driver: DRV8833RTYR with hardware current regulation.
  • MCU: ATtiny404-SSNR, 14-pin SOIC, explicitly approved as a deviation from the original ATtiny202-SSNR reference baseline to provide GPIO margin for fault input, diagnostics, and future revisions.
  • PCB constraints for the later layout phase: 80 mm x 50 mm, 4 layers, 1.6 mm, 2 oz outer copper.
  • Explicit exclusions for this phase: no schematic capture, no PCB layout, and no Gerber generation.
The P28A is a 2.8 Ah typical, 3.6 V nominal cell with a 4.2 V charge voltage; its standard charge current is 2.8 A and maximum charge current is 6.0 A.
1. Block Diagram
Diagram



  
    
  
  
    
  


































"12 V 4 A Adapter"
"Input Protection and EMI Filter"
"BQ25798 Charger and NVDC Power Path"
"External node_2S BMS"
"2S1P P28A Battery Pack"
"System Power Node"
"TPS63070 Buck-Boost 6.0 V"
"DRV8833 Motor Driver"
"6 V Brushed DC Motor"
"Low-Current Logic Supply"
"ATtiny404-SSNR"
"10 k Linear Speed Pot"
"Red Charging LED via STAT"
"Green Full Status LED"
"Battery NTC"
2. Power Flow
Adapter present
  1. The 12 V adapter enters through reverse-polarity protection, surge/ESD protection, bulk capacitance, and an EMI input filter.
  2. BQ25798 regulates the system node and charges the 2S battery through the external BMS.
  3. System load receives priority under input-current or voltage limiting. The charger reduces battery charge current before allowing the system node to collapse; if charging reaches zero and the input remains overloaded, battery supplement mode supports the system load.
  4. The TPS63070 converts the system/battery node to regulated 6.0 V for the motor stage.
  5. The logic rail powers ATtiny404, indicator LEDs, potentiometer sensing, and status/fault interfaces.
Adapter absent
  1. The protected 2S battery supplies the BQ25798 system node through the charger power path.
  2. TPS63070 maintains the 6.0 V motor rail across the battery discharge range.
  3. Firmware commands a soft-start PWM ramp and disables the motor on charger, BMS, undervoltage, or driver fault conditions as observable by the MCU.
Current-limit confirmation
BQ25798 has a maximum programmable IINDPM limit of 3.3 A, and its power management accounts for both system load and battery charging.
At the worst normal operating point used for planning:
  • Battery charge output: 8.4 V x 2.8 A = 23.52 W.
  • Estimated charger input at 90% efficiency: 26.13 W.
  • Motor output: 6.0 V x 0.70 A = 4.20 W.
  • Estimated motor-converter input at 90% efficiency: 4.67 W.
  • Logic and control allowance: 0.50 W.
  • Total adapter input estimate: 31.30 W / 12 V = 2.61 A.
Therefore the 3.3 A charger input limit is sufficient for the 2.8 A charge target plus the specified running load at nominal 12 V, with approximately 0.69 A programmed-limit margin. The 4 A adapter rating supplies source margin, but BQ25798 still caps usable input current at 3.3 A. Firmware/configuration must permit dynamic charge-current reduction when motor startup, adapter droop, thermal regulation, or other transient demand requires it.
3. Component Architecture
Input and charging
  • Locking DC input connector rated at least 5 A and at least 20 V.
  • Replaceable fuse or suitably selected resettable protection, reverse-polarity MOSFET, TVS diode, common-mode/differential filtering as required by conducted-emissions testing, and local bulk capacitance.
  • BQ25798RQMR as the buck-boost charger and NVDC power-path controller.
  • Charger support network per the final TI reference design: switching inductors, input/system/battery MLCC plus bulk capacitance, BATP/BATN Kelvin sensing, TS network for the battery NTC, and I2C pull-ups.
  • External BMS remains the cell-level protection and balancing layer. The PCB charger must connect to the BMS pack terminals, not directly bypass protected pack terminals.
Motor power and drive
  • TPS63070RNMR adjustable buck-boost set to 6.0 V. Its specified input range is 2.0-16 V and adjustable output range is 2.5-9 V, so the required 2S operating range and 6.0 V rail are within its voltage envelope.
  • DRV8833RTYR dual H-bridge; use one bridge for the fan motor and define unused-bridge inputs and outputs safely rather than leaving control inputs floating.
  • Motor connector, local ceramic and bulk decoupling, short high-current loops, and optional motor-terminal suppression footprint (RC snubber or bidirectional TVS) to be populated after motor EMI characterization.
Control and user interface
  • ATtiny404-SSNR is a 14-pin SOIC device.
  • Reserve PA0 exclusively for UPDI programming/debug.
  • The remaining pin set PA1-PA7 and PB0-PB3 provides eleven digital-capable pins, adequate for the seven listed signal functions plus reasonable control margin.
  • Proposed allocation:

Table

Physical pinMCU pinFinal function
1VDD3.3V
2PA4SPARE_1, reserved LOW_BATT_LED
3PA5SPARE_2, reserved future use
4PA6SPEED_ADC
5PA7GREEN_LED
6PB3SPARE_3
7PB2SPARE_4
8PB1I2C_SDA
9PB0I2C_SCL
10PA0UPDI
11PA1BQ25798_INT, optional hardware fault interrupt
12PA2SPARE_5, reserved UART TX debug
13PA3MOTOR_PWM
14GNDGround
TWI0 maps SDA/SCL to PB1/PB0, PA3 supports a TCA0 waveform output, and PA4 supports ADC0 AIN4.
  • Interpret “I2C x2” as the two I2C signal pins, SDA and SCL. ATtiny404 exposes one TWI0 hardware peripheral, not two independent hardware I2C controllers.
  • Read charger status and faults through BQ25798 I2C registers. Drive the red charging LED directly from BQ25798 STAT using the finalized 1.0k ohm, 1% network; it does not consume an MCU pin.
  • 10 k linear potentiometer across the logic rail and ground, with wiper RC-filtered into the ADC.
  • Target approximately 20 kHz PWM, with firmware soft-start, minimum usable duty threshold, stall timeout, and fault recovery policy.
4. Critical Calculations
Battery energy and runtime envelope
  • Nominal stored energy: 7.2 V x 2.8 Ah = 20.16 Wh.
  • Motor electrical load at the specified ceiling: 6.0 V x 0.70 A = 4.20 W.
  • Planning input load with 92% TPS63070 efficiency and 0.30 W control overhead: 4.20 / 0.92 + 0.30 = 4.87 W.
  • Idealized nominal runtime: 20.16 / 4.87 = 4.14 hours.
  • Practical expected full-speed runtime planning range: 3.3-4.0 hours, allowing for converter losses, BMS cutoff, wiring loss, cell aging, temperature, blade aerodynamic loading, and the fact that usable energy depends on discharge rate and cutoff voltage.
This is not a guaranteed product runtime. Final runtime must be measured with the actual motor, 9-inch blade, grille, pack, and final firmware.
Adapter and charger headroom
  • Adapter rating: 12 V x 4 A = 48 W.
  • BQ25798 programmed-input ceiling: 12 V x 3.3 A = 39.6 W nominal.
  • Estimated simultaneous charge plus run demand: 31.3 W or 2.61 A at 12 V.
  • Programmed-input power margin at nominal input: approximately 8.3 W.
  • Charge target is 1C for the 2.8 Ah cell and matches the P28A standard charge-current specification.
DRV8833 current regulation
DRV8833 uses:
RISENSE=0.2 VICHOPR_{ISENSE}=\frac{0.2\text{ V}}{I_{CHOP}}
The nominal resistor for 0.70 A is:
RISENSE,NOM=0.20.70=0.286 ΩR_{ISENSE,NOM}=\frac{0.2}{0.70}=0.286\ \Omega
The device trip threshold is specified from 160 mV to 240 mV, not an exact 200 mV. Therefore 0.287 ohm or 0.300 ohm, 1% does not guarantee 0.70 A maximum worst case. For example, 0.300 ohm at -1% combined with 240 mV threshold can trip at approximately 0.808 A.
To guarantee no more than 0.70 A using the specified 240 mV maximum threshold and a 1% resistor:
RNOM≥0.2400.70×0.99=0.3463 ΩR_{NOM}\geq\frac{0.240}{0.70\times0.99}=0.3463\ \Omega
Selection:
  • Minimum recommended: 0.348 ohm, 1%, low-inductance, appropriately rated.
  • Preferred margin choice: 0.360 ohm, 1%. The nominal 200 mV trip current is approximately 0.556 A; the worst-case high-threshold/minimum-resistance trip is approximately 0.673 A.
  • Resistor dissipation at 0.70 A is about 0.176 W for 0.36 ohm. Use at least a 0.5 W part with pulse capability and Kelvin routing to xISEN/GND.
Because the threshold tolerance is wide, this conservative hardware limit may reduce available starting torque. If the real fan cannot start reliably, the architecture must be revisited rather than increasing the guaranteed current above the requirement silently.
PWM
At a 20 MHz peripheral clock, a 20 kHz single-slope PWM period requires 1000 timer counts before prescaling considerations. Final timer mode, prescaler, resolution, and duty ramp will be fixed during firmware definition.
5. Major Design Risks

Table

RiskConsequenceMitigation / closure test
Motor startup or stall current exceeds 0.70 AFailure to start, repeated current chopping, overheatingTest actual motor/blade/grille across battery voltage and temperature; confirm torque with conservative 0.348/0.36 ohm sense value
DRV8833 threshold tolerance overlookedCurrent exceeds requirementDesign to 240 mV maximum threshold and resistor minimum, not nominal equation only
TPS63070 transient or thermal margin inadequate6 V droop, reset, reduced torqueMeasure switch current, efficiency, rail droop, and case/board temperature at startup, stall, low battery, and high ambient
Charger thermal regulation at 2.8 ACharge time increases; board hot spotFollow TI layout, maximize thermal copper/vias, validate worst-case adapter and ambient temperature
Adapter voltage/cable droopInput DPM reduces charge currentQualify adapter and cable; set VINDPM/IINDPM intentionally; capture input during motor start
Simultaneous charge and motor load exceeds assumptionsCharge throttling or supplement modeFirmware accepts dynamic charge reduction; validate 2.61 A estimate and startup transients
BMS and charger protection interactionsUnexpected cutoff or recovery loopsObtain exact BMS thresholds, delay times, NTC arrangement, and pack wiring before schematic approval
Brushed-motor EMI corrupts ADC/I2C/MCUSpeed instability, resets, false faultsSegregated layout, local suppression, filtered ADC, ground strategy, conducted/radiated testing
Battery temperature sensing is mechanically poorUnsafe or nuisance charge suspensionBond correct NTC to a cell body; verify TS thresholds and open/short detection
Single combined fault input hides root causeWeak diagnosticsPrefer separate charger status/interrupt and motor fault inputs using available spare pins
Actual blade/grille loading unknownRPM, current, acoustic, and runtime missFinal acceptance only with production-intent 9-inch blade and grille
2 oz, four-layer fabrication details not fixedImpedance to assembly and thermal variabilityLock stackup, copper thickness, via capability, and assembly rules before layout
6. Schematic Block Hierarchy
  1. Power Entry and Protection
    • DC jack/connector
    • Fuse or protection device
    • Reverse-polarity stage
    • TVS and EMI filter
    • Input bulk and high-frequency bypass
  2. BQ25798 Charger and NVDC Power Path
    • Power stage and inductors
    • Input/system/battery capacitors
    • BATP/BATN sensing
    • I2C and status/interrupt
    • Battery NTC/TS network
    • Charge-enable and reset defaults
  3. External Battery and BMS Interface
    • Pack positive/negative connector
    • NTC contacts
    • Optional pack-ID contact
    • Clearly documented protected-terminal wiring
  4. 6.0 V Buck-Boost Motor Supply
    • TPS63070 power stage
    • Feedback divider
    • Mode/enable control
    • Input/output bulk and ceramics
    • Rail test point
  5. Motor Driver and Motor Interface
    • DRV8833
    • 0.348 or 0.360 ohm, 1% sense resistor
    • Motor connector
    • Local bulk capacitance
    • Suppression footprints
    • Fault and enable/PWM interface
  6. MCU and Logic Supply
    • ATtiny404-SSNR
    • Logic regulator or validated charger-derived logic rail
    • Decoupling
    • UPDI connector and reset/programming provisions
    • I2C pull-ups
  7. User Interface
    • 10 k speed potentiometer and ADC filter
    • Charge/full/fault LED drivers and current limiting
    • Optional power or mode switch interface
  8. Test and Production Access
    • Adapter input, SYS, BAT, 6 V, logic rail, GND
    • UPDI
    • I2C SDA/SCL
    • PWM and nFAULT
    • Motor outputs and current-sense node with safe probing geometry
7. PCB Placement Zones
The later 80 mm x 50 mm board should use functional zoning; this is a placement plan only, not a PCB layout.
Diagram



  
    
  
  
    
  
















"Zone A: Adapter Connector and Protection"
"Zone B: BQ25798 Power Stage"
"Zone C: Battery and BMS Connector"
"Zone D: TPS63070 6 V Power Stage"
"Zone E: DRV8833 and Motor Connector"
"Zone F: Logic Supply and ATtiny404"
"Zone G: Potentiometer LEDs and UI Connector"
"Zone H: UPDI and Test Access"
  • Zone A - board edge: adapter connector, fuse/protection, TVS, and input bulk. Keep surge currents away from logic.
  • Zone B - adjacent to Zone A: BQ25798, its inductors, switching capacitors, and thermal-via field. Minimize high di/dt loops and preserve Kelvin battery sensing.
  • Zone C - board edge: battery/BMS connector near charger BAT path, physically keyed and polarity marked.
  • Zone D - central power corridor: TPS63070 with inductor and ceramic capacitors packed around the IC according to the datasheet layout pattern.
  • Zone E - motor edge: DRV8833, sense resistor, motor bulk capacitor, suppression footprint, and motor connector. Keep motor output copper short and distant from ADC/UPDI/I2C.
  • Zone F - quiet area: logic supply and ATtiny404, separated from both switching nodes and motor outputs by continuous ground reference and distance.
  • Zone G - accessible edge: potentiometer/UI connector and LEDs, with the ADC RC filter next to the MCU pin rather than at the remote control.
  • Zone H - service edge: UPDI and test points accessible after assembly.
  • Use Layer 2 as a substantially continuous ground plane. Reserve uninterrupted return paths under control signals. Use inner-layer power distribution only where it does not force noisy-current return through the quiet logic zone.
  • Provide substantial copper and via arrays under exposed thermal pads. Final widths and via counts require stackup, copper-thickness, temperature-rise, and fabricator capability checks.
8. Validation Plan
A. Documentation and design review
  • Confirm exact BMS model, thresholds, connector pinout, NTC value/B-constant, and recovery behavior.
  • Confirm exact motor part, winding resistance, no-load current, startup current, stall current, and rated operating point.
  • Review every charger, converter, MCU, and driver pin against current datasheets.
  • Independently review the schematic before layout; require no unresolved critical ERC issues.
B. Power-off checks
  • Inspect polarity, creepage/clearance, solder bridges, and thermal-pad soldering.
  • Measure resistance from each rail to ground and between battery/adapter domains.
  • Verify current-sense resistor value with a four-wire method if practical.
C. Staged power-up
  1. Power logic rail from a current-limited bench supply; program and verify UPDI.
  2. Bring up BQ25798 from a current-limited 12 V source without a battery; verify SYS behavior and I2C communication.
  3. Connect a battery simulator or protected pack; verify 8.4 V regulation, precharge/fast-charge/termination behavior, NTC hot/cold/open/short handling, and BMS interaction.
  4. Bring up TPS63070 into an electronic load; sweep input across the permitted 2S range and output load from zero to beyond 0.70 A transiently while observing regulation, ripple, efficiency, and thermal behavior.
  5. Bring up DRV8833 with an electronic/dummy motor load before connecting the production motor.
D. Current-limit verification
  • Sweep motor/load current and temperature while measuring the actual chopping threshold.
  • Verify every tested board remains at or below 0.70 A under maximum trip-threshold tendency and minimum sense resistance.
  • Test startup with 0.348 ohm and 0.360 ohm options; approve only a value that meets both current safety and mechanical start requirements.
  • Validate stall behavior, retry policy, driver fault assertion, and surface temperatures.
E. Simultaneous operation
  • Run the motor at maximum commanded speed while charging at the 2.8 A target.
  • Measure adapter voltage/current, BQ25798 input current, battery current, SYS voltage, 6 V rail, and temperatures.
  • Confirm normal steady-state input is near the planned 2.61 A and remains below 3.3 A.
  • Force input droop and overload; confirm charge current reduces first and supplement mode behaves safely.
F. Firmware and user interface
  • Verify approximately 20 kHz PWM frequency and duty resolution.
  • Verify monotonic pot-to-speed mapping, ADC noise rejection, soft start, minimum-start duty, controlled stop, and fault latching/recovery.
  • Verify charge, full, and fault indications in every charger/BMS state.
  • Verify watchdog recovery and brownout behavior during motor transients.
G. Mechanical load and product acceptance
  • Use the actual production-intent 6 V motor, 9-inch blade, grille, bearings, and airflow restrictions.
  • Measure loaded RPM across pot range, battery state of charge, adapter/no-adapter operation, and temperature.
  • Acceptance target: 2000-3000 RPM where intended without violating the 0.70 A current ceiling.
  • Measure full-speed battery runtime; compare against the 3.3-4.0 hour planning range.
  • Perform blocked-rotor, repeated-start, and long-duration endurance testing.
H. EMI, thermal, and reliability
  • Probe switching-node ringing, motor-terminal transients, ADC noise, I2C integrity, and MCU reset events.
  • Perform conducted and radiated pre-compliance scans with worst-case PWM duty and charger state.
  • Thermal-soak at minimum and maximum intended ambient with simultaneous charging and motor operation.
  • Test adapter insertion/removal, battery connection/disconnection, reverse input attempt, ESD at accessible controls/connectors, and BMS cutoff/recovery.
Approval Gate
No schematic, PCB layout, routing, or manufacturing files will be created until this engineering plan is approved.
Open Items, Closures, and Approved Deviations - Final Review
Closed: connector interfaces
Use polarized or latching production connectors except where the specified barrel jack defines the interface.

Table

ConnectorFunctionPinout
J112 V DC input, center-positive barrel jackPin 1 = +12V center; Pin 2 = GND
J2Main protected battery interfacePin 1 = BAT+; Pin 2 = BAT-
J3BMS cell-sense/service interfacePin 1 = B-; Pin 2 = B1 mid-tap; Pin 3 = B+
J4MotorPin 1 = MOTOR+; Pin 2 = MOTOR-
J5UPDIPin 1 = 3.3V; Pin 2 = UPDI; Pin 3 = GND
J614-pin manufacturing test headerGND, VBUS, PMID, SYS, BAT+, 6V_MOTOR, 3V3, SDA, SCL, TS, MOTOR_PWM, MOTOR_CURRENT_SENSE, UPDI, GND
J3 is exclusively a cell-tap service interface for a standard external 2S BMS architecture. B-, B1, and B+ must not be routed into any other PCB circuitry.
Closed: battery NTC definition
  • Use a 10k NTC, 103AT-class thermistor physically attached to the battery pack.
  • Derive the BQ25798 TS/JEITA resistor network using the current official TI datasheet equations and 1% resistor values during schematic design.
  • Route TS as a quiet analog signal, separated from charger switching nodes, converter switching nodes, motor outputs, and motor-current return paths.
Open: external BMS selection
  • Required function: generic external 2S Li-ion BMS, 5 A minimum and 10 A preferred, with balancing, overcharge, overdischarge, overcurrent, and short-circuit protection; temperature protection is preferred.
  • REQUIRES HUMAN SELECTION: the exact commercial BMS module MPN, thresholds, delay times, MOSFET resistance, connector arrangement, temperature behavior, and recovery behavior remain open.
  • The board must interface through protected pack terminals at J2. J3 provides cell taps only and must not duplicate charger or monitoring circuitry.
Closed: ambient and thermal validation range
  • Intended environment: indoor consumer product, 0 C to 40 C ambient.
  • Simultaneous charging plus motor operation must be thermally validated at 25 C nominal, 35 C minimum-required hot test, and 40 C worst-case target.
  • Pass/fail limits must include IC junction estimates, connector and inductor temperature rise, battery-cell temperature, enclosure airflow, charge-current throttling, and motor-rail regulation.
Open: motor characterization
  • REQUIRES PHYSICAL VALIDATION: exact stall current, winding inductance, loaded current/RPM curve, startup torque, EMI behavior, acoustic behavior, and final runtime require the production motor, 9-inch blade, and grille.
  • Until physical data exists, use 2.5 A assumed stall current only for transient component, connector, copper, bulk-capacitance, and protection robustness checks.
  • The 2.5 A assumption does not override the required DRV8833 hardware-regulated motor-current ceiling. Starting behavior must be proven with the conservative current-limit resistor and production mechanical load.
Closed: approved MCU and finalized pin map
ATtiny404-SSNR is approved for the BOM baseline as an explicit deviation from the original ATtiny202-SSNR reference specification. The reason is retained GPIO margin for a hardware fault input, diagnostics, service access, and future revisions.
The requested physical package numbering is verified: pin 1 VDD, pin 2 PA4, pin 3 PA5, pin 4 PA6, pin 5 PA7, pin 6 PB3, pin 7 PB2, pin 8 PB1, pin 9 PB0, pin 10 PA0/UPDI, pin 11 PA1, pin 12 PA2, pin 13 PA3, and pin 14 GND.
However, the requested signal assignment PA1 = SDA and PA2 = SCL is not supported by the current official ATtiny404 multiplexing table. Hardware TWI0 maps SDA to PB1 at physical pin 8 and SCL to PB0 at physical pin 9. BQ25798 INT exists as pin 21 and is an open-drain interrupt output.
Final approved pin map:

Table

Physical pinMCU pinProposed function
1VDD3.3V
2PA4SPARE_1, reserved LOW_BATT_LED
3PA5SPARE_2, reserved future use
4PA6SPEED_ADC
5PA7GREEN_LED
6PB3SPARE_3
7PB2SPARE_4
8PB1I2C_SDA
9PB0I2C_SCL
10PA0UPDI
11PA1BQ25798_INT, optional hardware fault interrupt
12PA2SPARE_5, reserved UART TX debug
13PA3MOTOR_PWM
14GNDGND
PA3 is verified as a TCA0 waveform-output pin suitable for MOTOR_PWM.
Hardware TWI0 is mandatory for BQ25798 communication. This MCU and pin-map decision is fully closed; do not alter it without explicit approval.
The rejected reduced-cost alternative was electrically feasible on ATtiny202-SSNR:

Table

FunctionATtiny202 pin
UPDIPA0
I2C SDAPA1
I2C SCLPA2
Motor PWMPA3
Speed ADCPA6
Green/full LEDPA7
This mapping is valid, but it consumes every non-supply pin and leaves zero GPIO margin. BQ25798 STAT is an open-drain hardware charge-status output that can drive an LED and indicates charging, completion/disabled states, and charge-suspend faults without consuming an MCU GPIO.
Approved decision: retain ATtiny404-SSNR. ATtiny202 is sufficient only for the frozen six-signal allocation and has no room for a separate motor fault input, charger interrupt, tachometer, power control, service input, or later diagnostics. Do not revert to ATtiny202 without a new explicit approval.
Closed: red charging LED circuit
BQ25798 STAT is an open-drain output that sinks while charging and can drive an LED.
Final network:
  • Retain the datasheet-required 10k ohm STAT pull-up to 3.3 V.
  • Add a parallel indicator branch: 3.3 V -> 1.0k ohm, 1% -> red LED anode; red LED cathode -> STAT.
  • Use a standard red indicator LED with nominal forward voltage 2.0 V.
Using a 0.2 V planning value for the low STAT voltage, an exact 1.0 mA target would calculate to 1.1k ohm. The approved final 1.0k ohm, 1% value intentionally gives approximately 1 mA:
ILED=3.3 V−2.0 V−0.2 V1.0 kΩ=1.10 mAI_{LED}=\frac{3.3\text{ V}-2.0\text{ V}-0.2\text{ V}}{1.0\text{ k}\Omega}=1.10\text{ mA}
At the guaranteed 0.4 V maximum STAT low level, the LED current is:
ILED,MIN=3.3 V−2.0 V−0.4 V1.0 kΩ=0.90 mAI_{LED,MIN}=\frac{3.3\text{ V}-2.0\text{ V}-0.4\text{ V}}{1.0\text{ k}\Omega}=0.90\text{ mA}
STAT is LOW while charging, so this pull-up LED topology lights during charging as required. The 10k pull-up contributes approximately 0.31 mA at a 0.2 V STAT low level, so total nominal STAT sink current is approximately 1.41 mA. The datasheet guarantees STAT low at a 5 mA sink-current test condition, providing comfortable margin for this load. LED resistor dissipation is approximately 1.21 mW; a standard 0.063 W or higher resistor is adequate.
This value is final for the engineering plan. LED brightness and color-bin variation remain subject to visual validation on the assembled product, but the nominal resistor must not be changed silently.
Closed: fuse assumptions
  • F1 remains 4 A. It exceeds the 2.5 A conservative motor-stall transient assumption by 1.5 A and also remains above the estimated 2.61 A nominal simultaneous adapter demand. Final fuse time-current behavior must tolerate motor startup and charger input transients.
  • The battery fuse remains 5 A. It provides 2x margin over the 2.5 A upstream transient assumption while remaining below the preferred 10 A BMS current class.
  • The 2.5 A assumption is used only for upstream fuse, BMS OCP, connector, and transient robustness sizing. DRV8833 current regulation with the approved 0.348-0.360 ohm sense-resistor range remains the real-time motor-current limiter at or below 0.70 A.
Standing rules for future phases
  • Always use the current official manufacturer datasheet; do not rely on a previously claimed revision date.
  • Do not copy BQ25798 register hexadecimal values from previous drafts. Recalculate every field and final register encoding from the current official TI datasheet when configuration is implemented.
  • Keep the exact BMS module and all motor performance claims visibly marked as unresolved until human selection or physical validation closes them.
  • No schematic, PCB layout, routing, or Gerber generation is authorized at this checkpoint.

  • Design Basis

  • 1. Block Diagram

  • 2. Power Flow

  • Adapter present

  • Adapter absent

  • Current-limit confirmation

  • 3. Component Architecture

  • Input and charging

  • Motor power and drive

  • Control and user interface

  • 4. Critical Calculations

  • Battery energy and runtime envelope

  • Adapter and charger headroom

  • DRV8833 current regulation

  • PWM

  • 5. Major Design Risks

  • 6. Schematic Block Hierarchy

  • 7. PCB Placement Zones

  • 8. Validation Plan

  • A. Documentation and design review

  • B. Power-off checks

  • C. Staged power-up

  • D. Current-limit verification

  • E. Simultaneous operation

  • F. Firmware and user interface

  • G. Mechanical load and product acceptance

  • H. EMI, thermal, and reliability

  • Approval Gate

  • Open Items, Closures, and Approved Deviations - Final Review

  • Closed: connector interfaces

  • Closed: battery NTC definition

  • Open: external BMS selection

  • Closed: ambient and thermal validation range

  • Open: motor characterization

  • Closed: approved MCU and finalized pin map

  • Closed: red charging LED circuit

  • Closed: fuse assumptions

  • Standing rules for future phases