Cryogenic SNSPD Readout

Worked for 42 sec

The stale size conflict was real but not the only cause. The remaining suspect is the hand-authored custom stackup, which contains duplicate wildcard hole definitions; I’m normalizing the board to Flux’s validated PCBWay 4 Layer template while preserving the exact 60 × 42 mm outline and every component position.

Worked for 2 mins 29 sec

flux

The outline and PCBWay stackup are now normalized, but validation still fails. The remaining likely cause is the six standalone plated through-hole pads with no net/terminal binding—ordinary DRC accepts them, but board validation does not.

Proposed fix: convert MH1–MH6 to 3.2 mm non-plated mounting holes at their exact current coordinates. RF placement and routing remain untouched. Confirm this mechanical change.

fatenerris

Can you add some stitching GND vias around the the board? Ionly see three.

Thought for 8 sec

flux

I’ll inspect the current ground copper and existing via coordinates, then add a perimeter/connector stitching pattern with conservative spacing and verify every inserted via’s read-back position before running DRC.

Worked for 2 mins 13 sec

flux

The vias landed at the requested coordinates; six collided with the large mounting/mechanical pads rather than collapsing. I’m removing only those six and replacing them with four clear top/bottom-edge vias between the mounting holes.

Worked for 1 min 29 sec

flux

Added 10 new GND stitching vias along the clear top, bottom, and left board perimeter. The layout now contains 16 GND smart vias total, with 0 airwires, 0 dangling traces, and no via/copper DRC violations.

Check board validation

Add SMA via fences

Run impedance review

Prepare PCBWay export

Files

Schematic

Layout

3D View

Schematic Verification

Scope status

Completed — electrical topology: OPA855 non-inverting DC-coupled amplifier, feedback/load/termination network, split-rail ferrite filtering, all six specified capacitors, SMA I/O, 1×3 power connector, and three requested test points.
Completed — connectivity: 20 schematic items (19 physical components plus one no-footprint safety annotation), 8 nets. U1 NC is explicitly no-connect; exposed pad is connected to V-_FILT; PD is tied high to V+_FILT; all connector shields and capacitor returns connect to GND.
Completed — ERC/connectivity review: final electrical and manufacturing review queries returned no open warning/error checks. Direct net inspection confirmed all required memberships.
Completed — supply safety annotation: the external rails remain capable of reproducing the paper experiment. A no-footprint schematic annotation and matching U1/J3 Role Details explicitly state that the current OPA855 absolute maximum is 5.5 V total and that ±4.9 V is controlled cryogenic experimental over-voltage, not room-temperature operation.
Failed — final readable schematic arrangement: components and nets were created correctly, but the available mutation interface did not expose schematic symbol placement/rearrangement. The rendered schematic remains spatially scattered and does not meet the requested left-to-right readability criterion. No PCB placement or routing was started.

Verified OPA855 details

Current TI datasheet: https://www.ti.com/lit/ds/symlink/opa855.pdf

Package: DSG WSON-8, 2.0 × 2.0 mm, 0.50 mm pitch, exposed pad.
Pin mapping: 1 FB, 2 NC, 3 IN−, 4 IN+, 5 VS−, 6 OUT, 7 VS+, 8 PD, exposed pad.
NC pin 2 must float.
Exposed pad must connect to VS−.
FB is internally connected to OUT and is intended for the feedback resistor connection.
PD high enables normal operation; it is tied to the filtered positive supply.
High-frequency bypassing must be close to the supply pins; C5/C6 provide the paper-matched 10 nF C0G bypasses.

Selected physical parts and footprints

Table

Ref(s)	Selection	MPN	Footprint/package
U1	TI OPA855	OPA855IDSGT	WSON-8 2.0×2.0 mm, 0.50 mm pitch, exposed pad
J1, J2	Amphenol RF 50 Ω edge-launch SMA jack	132255-11	Manufacturer/library board-edge end-launch footprint
J3	Samtec 1×3 male header	TSW-103-07-G-S	Through-hole, 2.54 mm pitch, single row
L1, L2	Sunlord 600 Ω @ 100 MHz ferrite bead	GZ1608D601TF	0603 / 1608 metric
TP1–TP3	Harwin SMT test point	S2761-46R	1.6 × 0.8 mm SMT footprint
R1	Panasonic thin-film 453 Ω, 0.1%, 0.1 W	ERA-3AEB4530V	SMD 0603 / 1608 metric
R2	Panasonic thin-film 75 Ω, 0.1%, 0.1 W	ERA3AEB750V	SMD 0603 / 1608 metric
R3	Panasonic thin-film 200 Ω, 0.1%, 0.1 W	ERA3AEB201V	SMD 0603 / 1608 metric
R4	Vishay thin-film 50 Ω, 0.1%, 0.1 W	P0603E50R0BBT	SMD 0603 / 1608 metric
C1–C4	Murata 100 nF, C0G/NP0, 50 V, 5%	GRM31C5C1H104JA01L	SMD 1206 / 3216 metric
C5–C6	Murata 10 nF, C0G/NP0, 50 V, 5%	GRM1885C1H103JA01D	SMD 0603 / 1608 metric

Final nets

VIN: J1 center, U1 IN+, R4.
VOUT: U1 OUT and FB, R1, J2 center, R3.
INV_FB: U1 IN−, R1, R2.
V+S_RAW: J3 pin 1 to L1.
V-S_RAW: J3 pin 3 to L2.
V+_FILT: L1, U1 VS+, U1 PD, C1, C2, C5, TP1.
V-_FILT: L2, U1 VS−, exposed pad, C3, C4, C6, TP2.
GND: J3 pin 2, SMA shields, R2/R3/R4 returns, C1–C6 returns, TP3.

Gain check

A_V = 1 + \frac{453}{75} = 7.04\ \text{V/V}

20\log_{10}(7.04) = 16.95\ \text{dB}

This is just above the OPA855 minimum stable gain of 7 V/V and matches the requested paper/LTspice value.

Remaining justified issues

The paper's high-voltage cryogenic operation remains outside the current TI recommended and absolute-maximum total supply ratings, but is now explicitly documented as a controlled research condition rather than an unresolved schematic defect.
The schematic requires a symbol-placement cleanup pass when schematic arrangement tooling is available. Connectivity and safety annotation are complete, but the current rendering is not presentation-ready.

Scope status
Verified OPA855 details
Selected physical parts and footprints
Final nets
Gain check
Remaining justified issues