Cryogenic SNSPD Readout

flux

The stale size conflict was real but not the only cause. The remaining suspect is the hand-authored custom stackup, which contains duplicate wildcard hole definitions; I’m normalizing the board to Flux’s validated PCBWay 4 Layer template while preserving the exact 60 × 42 mm outline and every component position.

flux

The outline and PCBWay stackup are now normalized, but validation still fails. The remaining likely cause is the six standalone plated through-hole pads with no net/terminal binding—ordinary DRC accepts them, but board validation does not.
Proposed fix: convert MH1–MH6 to 3.2 mm non-plated mounting holes at their exact current coordinates. RF placement and routing remain untouched. Confirm this mechanical change.
F

fatenerris

Can you add some stitching GND vias around the the board? Ionly see three.

flux

I’ll inspect the current ground copper and existing via coordinates, then add a perimeter/connector stitching pattern with conservative spacing and verify every inserted via’s read-back position before running DRC.

flux

The vias landed at the requested coordinates; six collided with the large mounting/mechanical pads rather than collapsing. I’m removing only those six and replacing them with four clear top/bottom-edge vias between the mounting holes.

flux

Added 10 new GND stitching vias along the clear top, bottom, and left board perimeter. The layout now contains 16 GND smart vias total, with 0 airwires, 0 dangling traces, and no via/copper DRC violations.
Check board validation
Add SMA via fences
Run impedance review
Prepare PCBWay export
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Files

Schematic

Layout

3D View

Project Specification
Project Overview
  • Status: Draft / implementation in progress
  • Cryogenic, DC-coupled, single-stage SNSPD readout amplifier based on the Texas Instruments OPA855 in WSON-8.
  • Reference implementation: Acta Physica Sinica 73 (2024) 138501 and the supplied LTspice files.
Intended Use
  • Read out fast electrical pulses from an SNSPD mounted in a cryostat.
  • Amplifier PCB operates nominally at the 40 K stage; experimental operation down to 4.2 K is documented by the paper.
  • Prototype/validation build rather than certified production hardware.
What the Device Should Do
  • Accept a DC-coupled SNSPD signal through a 50 Ω interface.
  • Provide approximately 7.04 V/V non-inverting gain (about 16.95 dB ideal; paper measured 16.7 dB).
  • Preserve multi-gigahertz pulse content with low parasitic loading.
  • Drive a 50 Ω measurement path through the paper's 200 Ω output loading arrangement.
Main Features
  • OPA855 wideband amplifier, minimum stable gain respected.
  • Split supply, nominally adjustable from ±2.5 V to ±4.9 V for cryogenic characterization.
  • Ferrite-bead rail filtering and mixed-value C0G/NP0 bypassing.
  • Coaxial signal input/output and separate positive/negative supply connections.
  • Four-layer FR4 layout optimized for short feedback and continuous signal returns.
System Architecture
Diagram



  
    
  
  
    
  
















SNSPD / 50 ohm coax input
50 ohm input termination
OPA855 non-inverting amplifier
200 ohm output load / coax output
Positive supply
Ferrite + C0G filtering
Negative supply
Ferrite + C0G filtering
Hardware Subsystems
Signal path
  • Non-inverting OPA855 configuration.
  • R1 = 453 Ω from OUT to IN−.
  • R2 = 75 Ω from IN− to ground.
  • R4 = 50 Ω from input node to ground.
  • R3 = 200 Ω from output node to ground, matching the reference circuit.
Power filtering
  • Positive and negative rails each pass through a 0603 ferrite bead.
  • C1–C4: 100 nF C0G/NP0, 1206.
  • C5–C6: 10 nF C0G/NP0, 0603, located immediately at OPA855 supply pins.
External interfaces
  • 50 Ω coax input, 50 Ω coax output.
  • Separate V+S, V−S, and ground connections suitable for cryostat wiring.
Interfaces and Connections

Table

InterfaceElectrical targetAssumption
VIN50 Ω single-ended, DC-coupledEdge-launch SMA unless physical constraints are later supplied
VOUT50 Ω measurement environmentEdge-launch SMA
V+S+2.5 V to +4.9 V nominalExternal low-noise supply
V−S−2.5 V to −4.9 V nominalExternal low-noise supply
GNDRF and supply returnContinuous reference plane except intentional local void
Power and Runtime Expectations
  • Externally powered; no battery or on-board regulation.
  • Reference performance at 40 K and ±4.9 V: approximately 8 mA total and 78 mW.
  • Reference performance at 4.2 K and ±4.9 V: approximately 6 mA and 58–63 mW depending on measurement condition.
Power Tree and Power Budget

Table

RailLoadTypical design currentDesign allocation
+V railOPA855 and bypass networkPart of 8 mA total at 40 K20 mA minimum connector/trace capacity
−V railOPA855 and bypass networkPart of 8 mA total at 40 K20 mA minimum connector/trace capacity
TotalAmplifier board8 mA at ±4.9 V, 40 K100 mA external supply limit recommended during bring-up
Manufacturing and Assembly Expectations
  • Four-layer FR4, nominal dielectric constant about 4.3.
  • OPA855 WSON-8 with exposed pad assembled by reflow.
  • Thin-film 0603 resistors; C0G/NP0 capacitors only for the paper-matched cryogenic passives.
  • Standard prototype fabrication; controlled-impedance 50 Ω traces to be finalized against the selected fab stackup.
Physical Design Expectations
  • Compact rectangular board with VIN and VOUT on opposite edges for straight signal flow.
  • Supply connector(s) away from the RF signal path.
  • OPA855, 10 nF decouplers, and feedback resistors form a very tight cluster.
  • Ground-plane copper void directly under OUT, IN−, R1, and R2 to reduce parasitic capacitance; no void under the main input/output transmission-line return path.
  • Ground via fence along RF routes and board perimeter, while preserving the intentional feedback-region void.
Important Design Decisions
  • Reproduce the paper's values instead of optimizing for a different gain.
  • Use a four-layer stack with top signal/components, inner-1 solid ground, inner-2 power distribution, and bottom secondary signal/ground.
  • Treat the SNSPD SPICE subcircuit as a simulation stimulus, not a physical PCB component.
  • Use physical connectors and footprints absent from LTspice so the circuit can be manufactured and tested.
Assumptions
  • Board operates primarily at 40 K and must tolerate room-temperature checkout.
  • ±4.9 V is an experimental cryogenic operating point reported by the paper; room-temperature operation must remain within the current OPA855 datasheet limits.
  • Edge-launch SMA connectors are acceptable because no cryostat connector or board-envelope constraints were provided.
  • A compact default outline will be selected after footprint placement.
  • Exact 50 Ω trace width requires the chosen PCB manufacturer's dielectric thickness and copper stackup; initial rules will use the Flux four-layer template and must be fab-tuned before manufacturing.
Validation Targets
  • Schematic connectivity matches the paper and LTspice source.
  • No unresolved critical ERC errors.
  • All components have manufacturable footprints.
  • Four-layer layout with zero airwires and no critical DRC violations.
  • Feedback loop has no vias and minimum practical length.
  • VIN/VOUT traces remain on one outer layer with continuous ground reference.
Change Notes
  • Initial specification created from the uploaded paper, LTspice schematic, SNSPD symbol, and SNSPD model library.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Signal path

  • Power filtering

  • External interfaces

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Validation Targets

  • Change Notes