BOM data fix J1 MPN

A

andsai

BOM data fix only, no layout or schematic changes.
J1 (5 V input, Molex Nano-Fit 2 pin): the footprint is 1053131202 (gold) and that is the part we buy. The Manufacturer Part Number property of J1 still reads 1053131102 (tin). Set the MPN of J1 to 1053131202, manufacturer Molex, and make any related part description text say gold contacts. Do not move, re-route or replace anything else.
Then confirm the new BOM line for J1 and that DRC/ERC results are unchanged.

flux

I’ll capture the current BOM and DRC/ERC state, update only J1’s metadata, then re-run both checks to confirm there is no design delta.

flux

J1’s purchasing metadata is corrected in place. I’m now verifying the generated BOM line and comparing fresh DRC/ERC results against the pre-change counts.

flux

Updated J1 BOM metadata only:
  • MPN: 1053131202
  • Manufacturer: Molex
  • Description/type: Wire-to-board / wire-to-wire connector, gold contacts
  • Footprint: CONN-TH_2P-P2.50_MOLEX_1053131202
  • Quantity: 1
No component replacement, connectivity, schematic geometry, routing, placement, or layout changes were made.
Fresh checks confirm results are unchanged: DRC remains at 18 errors and 35 warnings; ERC has no reported findings.
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Schematic

Layout

3D View

Power Design Notes
Implemented architecture
5V_IN_RAW enters through Molex 105430-1202, is clamped by bidirectional P6SMB6.8CA, and passes through TPS259470ARPWR to 5V_PROTECTED. The protected bus feeds two TPS62130AQRGTRQ1 bucks and an ADP121-AUJZ33R7 3.3 V LDO.
Source and load budget

Table

RailSizing caseOutput powerApproximate 5 V input contribution
3V81.5 A5.70 W1.27 A at 90% efficiency
1V83.0 A regulator capability5.40 W1.20 A at 90% efficiency
3V30.15 A LDO maximum0.495 W0.15 A
Combinedconservative maximum11.595 W outputabout 2.57 A, excluding small quiescent current
The conservative case remains below the approved 5 V / 3 A source with about 0.43 A margin. The intended initial case of 1.5 A on each camera rail is about 1.97 A from 5 V including the LDO maximum, leaving about 1.03 A margin for startup, losses, and later housekeeping.
The design calculations were independently re-evaluated with the project compute tool. Exact IC-level SPICE verification was not run because vendor switching-regulator and eFuse macromodels are not available to the simulator; an idealized behavioral model would not validate loop stability, protection timing, or switching behavior meaningfully.
E-fuse configuration
The TPS259470A UVLO and OVLO comparators use a 1.20 V typical threshold and the divider relationship VIN = 1.20 × (Rtop + Rbottom) / Rbottom.
  • R1 = 1.5 MOhm, R2 = 560 kOhm: UVLO rising threshold ≈ 4.414 V.
  • R3 = 1.5 MOhm, R4 = 374 kOhm: OVLO rising threshold ≈ 6.013 V.
  • R5 = 953 Ohm: current limit ≈ 3334 / 953 = 3.498 A.
  • C2 = 2.4 nF: typical active-current-limit blanking ≈ 1.51 × 2.4 / 1.8 = 2.01 ms.
  • C1 = 4.7 nF: typical output slew ≈ 2000 / 4700 = 0.426 V/ms.
  • ~FLT is exposed as EFUSE_FAULT with a 1 MOhm pull-up to 5V_IN_RAW; AUXOFF is intentionally no-connect.
The input TVS is bidirectional so applying reverse input polarity does not make the TVS itself a hard short. The eFuse input divider resistors are intentionally high to limit current into control pins during a negative input event.
3.8 V buck
  • U2 = TPS62130AQRGTRQ1, L1 = 2.2 uH Würth 74438356022.
  • Feedback: R7 = 300 kOhm, R8 = 80.0 kOhm, giving 0.8 × (1 + 300/80) = 3.800 V.
  • Input: C5 = 22 uF; AVIN bypass C6 = 100 nF.
  • Output: C7 + C8 = 44 uF nominal, selected to retain useful capacitance after DC bias.
  • Soft start: C9 = 10 nF, approximately 4 ms typical.
  • DEF is grounded for nominal output. FSW is pulled high from 5V_PROTECTED to select 1.25 MHz typical; high is the low-frequency state.
  • PGOOD_3V8 is pulled up to 3V8 with 100 kOhm.
1.8 V buck
  • U3 = TPS62130AQRGTRQ1, L2 = 2.2 uH Würth 74438356022.
  • Feedback: R10 = 100 kOhm, R11 = 80.0 kOhm, giving 0.8 × (1 + 100/80) = 1.800 V.
  • Input: C10 = 22 uF; AVIN bypass C11 = 100 nF.
  • Output: C12 + C13 = 44 uF nominal.
  • Soft start: C14 = 10 nF, approximately 4 ms typical.
  • DEF is grounded; FSW is high for 1.25 MHz typical.
  • PGOOD_1V8 is pulled up to 1V8 with 100 kOhm.
For both bucks, AVIN and PVIN share the same source, AVIN has its own 100 nF-to-AGND bypass, and AGND, both PGND pins, and EP are all on the common GND net as required.
3.3 V housekeeping rail
U4 = ADP121-AUJZ33R7 is permanently enabled from 5V_PROTECTED. C15 = 1 uF is the input bypass and C16 = 1 uF is the required low-ESR output capacitor. The rail is annotated for 150 mA maximum, while later service export is limited to 10 mA. NC is intentionally no-connect.
Rail monitoring
  • TP1: 5V_PROTECTED
  • TP2: 3V8
  • TP3: 1V8
  • TP4: 3V3
  • J2 pin 1: MON_3V8_DIV2, 10 kOhm / 10 kOhm, 1.9 V nominal.
  • J2 pin 2: MON_1V8_DIV2, 10 kOhm / 10 kOhm, 0.9 V nominal.
PCB-stage gates
  1. Author or validate the exact Molex 105430-1202 right-angle SMT footprint and mechanical courtyard from the manufacturer drawing.
  2. Author or validate the TI RPW HotRod QFN footprint for TPS259470ARPWR; the original Flux library symbol was reported because its duplicated terminals were incorrect.
  3. Place TVS and raw input capacitor directly at J1, then place U1 and protected bulk capacitor with the shortest possible high-current loop.
  4. Place each buck input capacitor at PVIN/PGND, keep SW copper compact, put the inductor adjacent to SW, and place feedback dividers at FB away from SW.
  5. Use solid ground planes and thermal vias under both TPS62130A exposed pads; the pad, AGND, and PGND connection is mandatory.

  • Implemented architecture

  • Source and load budget

  • E-fuse configuration

  • 3.8 V buck

  • 1.8 V buck

  • 3.3 V housekeeping rail

  • Rail monitoring

  • PCB-stage gates